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1. 发明授权

US5655100A Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system 失效
标题翻译：用于控制分组交换高速缓存一致多处理器系统中的存储器事务执行的事务激活处理器
公开(公告)号：US5655100A
公开(公告)日：1997-08-05
申请号：US414772
申请日：1995-03-31
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.
摘要翻译：多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。一些子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器以及相应的主缓存标签集（Etag），包括由高速缓冲存储器存储的每个数据块的一个Etag。每个数据处理器包括一个接口，用于向系统控制器发送存储器事务请求，并接收来自系统控制器的高速缓存事务请求，对应于其他数据处理器的存储器事务请求。系统控制器包括事务激活逻辑，用于当其满足预定义的激活准则时激活每个所述存储器事务请求，并且用于阻止每个所述存储器事务请求直到满足预定义的激活标准。活动事务状态表存储表示已激活的存储器事务请求的状态数据，包括每个激活的事务的地址值。事务激活逻辑包括比较器逻辑，用于将每个存储器事务请求与所有激活的存储器事务请求的活动事务状态数据进行比较，以便检测特定存储器事务请求的激活是否违反预定义的激活标准。对于回写事务有一些例外，用于访问映射到相同高速缓存行的未决事务，先前激活的事务的数据块的传入事务将被阻止，直到映射到同一高速缓存行的挂起事务完成。

2. 发明授权

US5684977A Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system 失效
标题翻译：回写取消处理系统，用于分组交换高速缓存一致多处理器系统
公开(公告)号：US5684977A
公开(公告)日：1997-11-04
申请号：US415040
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect. The transaction execution circuitry pipelines memory access requests from the data processors, and includes invalidation circuitry for processing each writeback request from a given data processor prior to activation to determine if the Dtag index corresponding to the victimized cache line is invalid. Thereafter, the invalidation circuitry activates writeback requests only if the Dtag index is not invalid and cancels the writeback request if the Dtag index is invalid.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应缓存存储器和一组主缓存标签（Etags），包括由高速缓存存储器存储的每个数据块的一个高速缓存标签。每个数据处理器包括用于向系统控制器发送存储器事务请求的主接口。系统控制器处理每个存储器事务，并为每个数据处理器维护一组重复的缓存标签（Dtags）。最后，系统控制器包含用于激活交易以进行互连维修的事务执行电路。交易执行电路管理来自数据处理器的存储器访问请求，并且包括用于在激活之前处理来自给定数据处理器的每个回写请求的无效电路，以确定与受害高速缓存行对应的Dtag索引是否无效。此后，无效电路仅在Dtag索引无效时才激活写回请求，如果Dtag索引无效则取消写回请求。

3. 发明授权

US5905998A Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system 失效
标题翻译：用于控制分组交换高速缓存一致多处理器系统中的存储器事务处理的事务激活处理器
公开(公告)号：US5905998A
公开(公告)日：1999-05-18
申请号：US858792
申请日：1997-05-19
申请人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
发明人： Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin Normoyle , Paul Loewenstein , Louis F. Coffin, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met. An active transaction status table stores status data representing memory transaction requests that have been activated, including an address value for each activated transaction. The transaction activation logic includes comparator logic for comparing each memory transaction request with the active transaction status data for all activated memory transaction requests so as to detect whether activation of a particular memory transaction request would violate the predefined activation criteria. With certain exceptions concerning writeback transactions, an incoming transaction for accessing a data block that maps to the same cache line a pending, previously activated transaction, will be blocked until the pending transaction that maps to the same cache line is completed.
摘要翻译：多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。一些子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器以及相应的主缓存标签集（Etag），包括由高速缓冲存储器存储的每个数据块的一个Etag。每个数据处理器包括一个接口，用于向系统控制器发送存储器事务请求，并接收来自系统控制器的高速缓存事务请求，对应于其他数据处理器的存储器事务请求。系统控制器包括事务激活逻辑，用于当其满足预定义的激活准则时激活每个所述存储器事务请求，并且用于阻止每个所述存储器事务请求直到满足预定义的激活标准。活动事务状态表存储表示已激活的存储器事务请求的状态数据，包括每个激活的事务的地址值。事务激活逻辑包括比较器逻辑，用于将每个存储器事务请求与所有激活的存储器事务请求的活动事务状态数据进行比较，以便检测特定存储器事务请求的激活是否违反预定义的激活标准。对于回写事务有一些例外，用于访问映射到相同高速缓存行的未决事务，先前激活的事务的数据块的传入事务将被阻止，直到映射到同一高速缓存行的挂起事务完成。

4. 发明授权

US5581729A Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system 失效
标题翻译：并行相干读写事务处理系统，用于分组交换高速缓存一致多处理器系统
公开(公告)号：US5581729A
公开(公告)日：1996-12-03
申请号：US414763
申请日：1995-03-31
申请人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Paul Loewenstein , Sue K. Lee , Louis F. Coffin III
发明人： Satyanarayana Nishtala , Zahir Ebrahim , William C. Van Loo , Paul Loewenstein , Sue K. Lee , Louis F. Coffin III
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0828 , G06F12/0822
摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor. Each data processor has a writeback buffer for storing the data block previously stored in a victimized cache line until its respective writeback transaction is completed and an Nth+1 Dtag for storing the cache state of a cache line associated with a read transaction which is executed prior to an associated writeback transaction of a read-writeback transaction pair. Accordingly, upon a cache miss, the interconnect may execute the read and writeback transactions in parallel relying on the writeback buffer or Nth+1 Dtag to accommodate any ordering of the transactions.
摘要翻译：提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。每个主缓存索引具有一组主缓存标签（Etags），包括缓存存储器存储的每个数据块的一个缓存标签。每个数据处理器包括具有用于向系统控制器发送存储器事务请求的主类的主接口。系统控制器包括用于由数据处理器处理每个存储器事务请求的存储器事务请求逻辑。系统控制器维护具有每个数据处理器的一组重复缓存标签（Dtags）的重复缓存索引。每个数据处理器具有用于存储先前存储在受害高速缓存行中的数据块的回写缓冲器，直到其各自的回写事务完成为止，以及用于存储与先前执行的读取事务相关联的高速缓存行的高速缓存状态的第N + 1个Dtag 到读写回事务对的相关回写事务。因此，在高速缓存未命中时，互连可以依赖于回写缓冲器或Nth + 1Dtag并行地执行读取和回写事务，以适应事务的任何排序。

5. 发明授权

US4366474A Identification of electric power network phases experiencing disturbances 失效
标题翻译：确定遇到干扰的电力网络阶段
公开(公告)号：US4366474A
公开(公告)日：1982-12-28
申请号：US253969
申请日：1981-04-13
申请人： Paul Loewenstein
发明人： Paul Loewenstein
IPC分类号： H02H3/34 , G01R27/16 , G01R29/16 , G01R31/02 , H02H7/26 , G08B21/00
CPC分类号： G01R27/16 , G01R29/16 , G01R31/021 , H02H7/26
摘要： A system for identifying which of the phases of an N-phase electric-power transmission network has experienced an electrical disturbance. For each phase there is produced a first signal representative of the transient variations of an electrical parameter of the respective phase, or of a linear combination of at least two of these parameters. A set of N second signals is generated from the product of two linear combinations of at least N-1 signals selected among the first signals. The sum of all coefficients for each linear combination is set to zero, with each of the second signals being related to a given phase. Each of the second signals is then integrated to produce a set of N third signals associated with the respective phases. A fourth signal is generated by combining all of the N first signals in a symmetrical manner with respect to all of the first signals, such that the fourth signal is independent of the associated phases. The fourth signal is compared with each of the third signals to produce comparison signals related to respective phases; the faulty phase is identified in accordance with the comparison signals thus produced.
摘要翻译：一种用于识别N相电力传输网络中的哪些相经历电气干扰的系统。对于每个相位，产生表示各相的电参数的瞬态变化的第一信号，或这些参数中的至少两个的线性组合。从第一信号中选择的至少N-1个信号的两个线性组合的乘积产生一组N个第二信号。每个线性组合的所有系数的和被设置为零，其中每个第二信号与给定的相位相关。然后，每个第二信号被积分以产生与各个相位相关联的一组N个第三信号。通过以全部第一信号的对称方式组合所有N个第一信号来产生第四信号，使得第四信号独立于相关联的相位。将第四信号与每个第三信号进行比较，以产生与相位相关的比较信号; 根据由此产生的比较信号来识别故障相位。

6. 发明申请

US20070255907A1 Value-based memory coherence support 有权
标题翻译：基于价值的记忆一致性支持
公开(公告)号：US20070255907A1
公开(公告)日：2007-11-01
申请号：US11413243
申请日：2006-04-28
申请人： Hakan Zeffer , Erik Hagersten , Anders Landin , Shailender Chaudhry , Paul Loewenstein , Robert Cypher , Zoran Radovic
发明人： Hakan Zeffer , Erik Hagersten , Anders Landin , Shailender Chaudhry , Paul Loewenstein , Robert Cypher , Zoran Radovic
IPC分类号： G06F13/28
CPC分类号： G06F12/0815 , G06F12/0808 , G06F12/0822 , G06F12/0897
摘要： In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.
摘要翻译：在一个实施例中，处理器包括相干陷阱单元和耦合到相干陷波单元的陷波逻辑。相干陷阱单元还被耦合以接收响应于处理器执行存储器操作而访问的数据。相干陷阱单元被配置为检测数据与指示要发起的相干陷阱的指定值相匹配以相干地执行存储器操作。陷阱逻辑被配置为响应于相干陷阱单元检测到指定值而陷入指定的软件例行程序。在一些实施例中，高速缓存中的高速缓存标签可以跟踪对应的高速缓存行是否具有指定值，并且可以使用高速缓存标签来响应对对应的高速缓存行的访问来触发陷阱。

7. 发明申请

US20070043915A1 CONDITIONAL MULTISTORE SYNCHRONIZATION MECHANISMS 有权
标题翻译：条件多重同步机制
公开(公告)号：US20070043915A1
公开(公告)日：2007-02-22
申请号：US11465376
申请日：2006-08-17
申请人： Mark Moir , Robert Cypher , Paul Loewenstein
发明人： Mark Moir , Robert Cypher , Paul Loewenstein
IPC分类号： G06F13/28
CPC分类号： G06F12/0864 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F12/0804 , G06F12/0815 , G06F12/0846
摘要： We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.
摘要翻译：我们提出一类机制来支持新的同步风格，为现有解决方案复杂，昂贵和/或其他不足的现有问题提供简单而有效的解决方案。通常，所提出的机制允许程序从第一存储器位置（称为“标记的”位置）读取，然后继续执行，将值存储到零个或多个其他存储器位置，使得这些存储器生效（即，变为只有当标记的存储器位置不改变时，才能在存储器系统中可见）在一些实施例中，机制还允许程序确定第一存储器位置何时改变。我们称提出的机制是条件多存储同步机制。

8. 发明授权

US6141692A Directory-based, shared-memory, scaleable multiprocessor computer system having deadlock-free transaction flow sans flow control protocol 失效
标题翻译：基于目录的共享存储器，可扩展的多处理器计算机系统具有无死锁事务流程，无流控制协议
公开(公告)号：US6141692A
公开(公告)日：2000-10-31
申请号：US674358
申请日：1996-07-01
申请人： Paul Loewenstein , Erik Hagersten
发明人： Paul Loewenstein , Erik Hagersten
IPC分类号： G06F12/08 , G06F15/16
CPC分类号： G06F12/0828 , G06F12/0813 , G06F2212/272
摘要： A method and apparatus are provided which eliminate the need for an active traffic flow control protocol to manage request transaction flow between the nodes of a directory-based, scaleable, shared-memory, multi-processor computer system. This is accomplished by determining the maximum number of requests that any node can receive at any given time, providing an input buffer at each node which can store at least the maximum number of requests that any node can receive at any given time and transferring stored requests from the buffer as the node completes requests in process and is able to process additional incoming requests. As each node may have only a certain finite number of pending requests, this is the maximum number of requests that can be received by a node acting in slave capacity from any another node acting in requester capacity. In addition, each node may also issue requests that must be processed within that node. Therefore, the input buffer must be sized to accommodate not only external requests, but internal ones as well. Thus, the buffer must be able to store at least the maximum number of transaction requests that may be pending at any node, multiplied by the number of nodes present in the system.
摘要翻译：提供了一种方法和装置，其消除了对主动业务流控制协议的需求，以管理基于目录的可扩展，共享存储器，多处理器计算机系统的节点之间的请求事务流。这通过确定任何节点在任何给定时间可以接收的最大请求数量来实现，在每个节点处提供输入缓冲器，其可以存储任何节点在任何给定时间可以接收的至少最大数量的请求并传送存储的请求当节点完成正在处理的请求并且能够处理其他传入请求时，从缓冲区中。由于每个节点可能只有一定数量的待处理请求，所以这个请求可以由从根据请求者能力的任何另一个节点以从属容量起作用的节点接收的最大请求数。此外，每个节点还可以发出必须在该节点内处理的请求。因此，输入缓冲区的大小必须不仅适合外部请求，还可以适应内部请求。因此，缓冲区必须能够存储至少可能在任何节点处挂起的事务请求的最大数目乘以系统中存在的节点数。

9. 发明申请

US20070043933A1 INSTRUCTION SET ARCHITECTURE EMPLOYING CONDITIONAL MULTISTORE SYNCHRONIZATION 有权
标题翻译：使用条件多重同步的指令集架构
公开(公告)号：US20070043933A1
公开(公告)日：2007-02-22
申请号：US11465383
申请日：2006-08-17
申请人： Mark Moir , Robert Cypher , Paul Loewenstein
发明人： Mark Moir , Robert Cypher , Paul Loewenstein
IPC分类号： G06F9/44
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30094 , G06F9/3861 , G06F12/0815
摘要： We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.
摘要翻译：我们提出一类机制来支持新的同步风格，为现有解决方案复杂，昂贵和/或其他不足的现有问题提供简单而有效的解决方案。通常，所提出的机制允许程序从第一存储器位置（称为“标记的”位置）读取，然后继续执行，将值存储到零个或多个其他存储器位置，使得这些存储器生效（即，变为只有当标记的存储器位置不改变时，才能在存储器系统中可见）在一些实施例中，机制还允许程序确定第一存储器位置何时改变。我们将所提出的机制称为条件多存储同步机制，并且定义与其一致的指令集架构的方面。

10. 发明授权

US4568872A Method of measuring the distance of a fault on a line taking account of distributed capacitances 失效
标题翻译：考虑分布电容测量线路故障距离的方法
公开(公告)号：US4568872A
公开(公告)日：1986-02-04
申请号：US497625
申请日：1983-05-24
申请人： Isabelle Heller , Paul Loewenstein
发明人： Isabelle Heller , Paul Loewenstein
IPC分类号： G01R31/08 , H02H7/26
CPC分类号： G01R31/085 , H02H7/265
摘要： The invention concerns a method of direct measurement of a parameter characterizing a fault on an electricity line 1, such as the distance x or the resistance R.sub.d of the fault, the method being based on Ohm's Law including the line inductance L and the resistances R, R.sub.d. The signals respectively associated with the variation of current i(t) and of voltage v(t) at the measuring point M are operated upon by transfer functions the ratio of which is equal to:(2/.tau.) tan .omega..tau./2,.tau. corresponding to the propagation time of a wave over double the distance between the measuring point M and a zone boundary P. The method thus takes into account the distributed capacitances C of the line.
摘要翻译：本发明涉及直接测量表征电力线1上的故障的参数的方法，例如故障的距离x或电阻Rd，该方法基于包括线路电感L和电阻R的欧姆定律，路分别与测量点M处的电流i（t）和电压v（t）的变化相关联的信号通过其比率等于：（2 /τ）tanωωτ/ 2的传递函数来操作， τ对应于波的传播时间超过测量点M和区域边界P之间的距离的两倍。因此该方法考虑了线的分布电容C。

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