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1. 发明授权

US09715907B1 Optimal data eye for improved Vref margin 有权
公开(公告)号：US09715907B1
公开(公告)日：2017-07-25
申请号：US15150334
申请日：2016-05-09
申请人： Invecas, Inc.
发明人： Venkata N. S. N. Rao , Ravindra Kantamani , Prasad Chalasani
IPC分类号： G11C7/22 , G11C11/4076 , G11C8/18 , G11C7/00 , G11C11/4096 , G11C5/06
CPC分类号： G06N99/005 , G11C5/063 , G11C7/00 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/10 , G11C29/36 , G11C2029/3602 , G11C2207/2254
摘要： An optimized method and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

2. 发明授权

US09613700B1 TCAM field enable logic 有权
公开(公告)号：US09613700B1
公开(公告)日：2017-04-04
申请号：US15183591
申请日：2016-06-15
申请人： Invecas, Inc.
发明人： Harold Pilo , Gerald P. Pomichter , Michael Lee , John Edward Barth, Jr.
IPC分类号： G11C15/00 , G11C15/04 , H03K19/177 , H03K19/00
CPC分类号： G11C15/04 , H03K19/0013 , H03K19/1776
摘要： A content addressable memory (“CAM”) field enabling logic comprises fields and field enable logics. The fields each have local match lines and a corresponding field enable control for enabling the respective field. The field enable logics are serially connected. Each of the fields is coupled to a corresponding one of the field enable logics via the respective local match lines. The corresponding field enable control for each of the fields is coupled to the corresponding one of the field enable logic and to any ones of the field enable logics that come after the corresponding one of the field enable logic along the serially-connected field enable logics.

3. 发明授权

US09564183B2 Sense amplifier having a timing circuit for a presearch and a main search 有权
标题翻译：具有用于预搜索和主搜索的定时电路的感测放大器
公开(公告)号：US09564183B2
公开(公告)日：2017-02-07
申请号：US14934050
申请日：2015-11-05
申请人： Invecas, Inc.
发明人： John Edward Barth, Jr.
IPC分类号： G11C15/04 , G11C7/06 , G11C7/08
CPC分类号： G11C7/067 , G11C7/08 , G11C15/04
摘要： A line sense amplifier comprises: a presearch block, a main search block, and a timing circuit. The presearch block is coupled to a presearch line for sensing the presearch line. The main search block is coupled to a main line for sensing the main line. The timing circuit operates the presearch block and the main search block for charging and sensing of the presearch line and the main line. The timing circuit initiates the main search block to determine a match condition for the main line based on whether a match condition is determined for the presearch line.
摘要翻译：线检测放大器包括：预搜索块，主搜索块和定时电路。预调查块与预检线相连接，用于感应预调线。主搜索块耦合到用于感测主线的主线。定时电路操作预搜索块和主搜索块，用于对预调线和主线进行充电和感测。定时电路基于是否为预调查线确定匹配条件，启动主搜索块以确定主线的匹配条件。

4. 发明授权

US10014866B2 Clock alignment scheme for data macros of DDR PHY 有权
公开(公告)号：US10014866B2
公开(公告)日：2018-07-03
申请号：US15707205
申请日：2017-09-18
申请人： Invecas, Inc.
发明人： Narasimhan Vasudevan , Venkata N. S. N. Rao , Prasad Chalasani
IPC分类号： H03L7/06 , H03L7/081 , G11C11/4063 , H03L7/083 , G11C7/22 , H03L7/091
CPC分类号： H03L7/0818 , G11C7/222 , G11C11/4063 , G11C11/4076 , H03L7/0812 , H03L7/083 , H03L7/085 , H03L7/089 , H03L7/091
摘要： A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.

5. 发明授权

US09946620B2 Memory built-in self test system 有权
公开(公告)号：US09946620B2
公开(公告)日：2018-04-17
申请号：US15012707
申请日：2016-02-01
申请人： Invecas, Inc.
发明人： Kevin W. Gorman , Thomas Chadwick , Nancy Pratt
IPC分类号： G11C29/00 , G01R31/28 , G06F11/263 , G11C29/16 , G11C29/14 , G11C29/04
CPC分类号： G06F11/263 , G11C29/14 , G11C29/16 , G11C2029/0401
摘要： A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.

6. 发明授权

US09564180B1 Deep-sleep wake up for a memory device 有权
标题翻译：深度睡眠唤醒记忆体设备
公开(公告)号：US09564180B1
公开(公告)日：2017-02-07
申请号：US15192697
申请日：2016-06-24
申请人： Invecas, Inc.
发明人： Harold Pilo , Michael Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/148
摘要： A memory device comprises memory banks, power gates, and bank wake-up circuits. Each of the memory banks has a core voltage supply. The power gates are coupled to the memory banks for charging the core voltage supplies and have a plurality of powering modes. The bank wake-up circuits are coupled to the power gates for selecting one of the plurality of power modes for charging the memory banks during a wake-up mode. The bank wake-up circuits sense the core voltage supplies during the wake-up mode. The bank wake-up circuits serially charge the memory banks as a function of the sensed core voltage supplies of the memory banks.
摘要翻译：存储器件包括存储器组，电源门和存储体唤醒电路。每个存储体都具有核心电压源。功率门耦合到存储器组，用于对核心电压源进行充电并具有多个供电模式。银行唤醒电路耦合到电源门，用于选择多个功率模式之一，以在唤醒模式期间对存储体充电。银行唤醒电路在唤醒模式下感测核心电压源。存储体唤醒电路根据感测到的存储体的核心电压电源对存储体串行充电。

7. 发明授权

US10094859B1 Voltage detector 有权
公开(公告)号：US10094859B1
公开(公告)日：2018-10-09
申请号：US15654598
申请日：2017-07-19
申请人： Invecas, Inc.
发明人： Venkata N. S. N. Rao , Prasad Chalasani , Majid Jalali Far
IPC分类号： G01R19/165
摘要： A power voltage detector comprises voltage sensors for sensing supply voltages; and a logic. The logic combines the sensed supply voltages to generate a logic output indicative of whether the sensed supply voltages have met one or more predefined thresholds. Each of the voltage sensors has diode-connected transistors and passive resistance. The diode-connected transistors and the passive resistance are serially connected for generating an output, where the output is coupled to an input of the logic.

8. 发明授权

US10061340B1 Bandgap reference voltage generator 有权
公开(公告)号：US10061340B1
公开(公告)日：2018-08-28
申请号：US15879355
申请日：2018-01-24
申请人： Invecas, Inc.
发明人： Venkata N. S. N. Rao , Majid Jalali Far
IPC分类号： G05F3/26 , H03F3/04 , H03K5/24 , G05F3/30
CPC分类号： G05F3/26 , G05F3/267 , G05F3/30 , H03F1/30 , H03F3/04 , H03F3/45183 , H03F2200/447 , H03K5/24 , H03K5/2481
摘要： A bandgap reference voltage generator, comprises: a bias circuit configured to generate a start signal; a startup circuit having at least two serially-connected transistors configured to receive the start signal; a proportional-to-absolute-temperature (“PTAT”) generation circuit having a first current mirror, an amplifier, a resistor, and transistors; and a complementary-to-absolute-temperature (“CTAT”) generation circuit having a second current mirror, a passive network of resistors, and at least one transistor. The at least two serially-connected transistors are connected across a first input of the amplifier and a second input of the amplifier. An output of the amplifier is coupled to the first current mirror and the second current mirror. The passive network of resistors is coupled across outputs of the second current mirror. The CTAT generation circuit has an output node for outputting a bandgap reference voltage.

9. 发明授权

US09865361B2 Diagnostics for a memory device 有权
公开(公告)号：US09865361B2
公开(公告)日：2018-01-09
申请号：US15140242
申请日：2016-04-27
申请人： Invecas, Inc.
发明人： Thomas Chadwick , Kevin W. Gorman , Nancy Pratt
IPC分类号： G11C29/00 , G11C29/38 , G11C29/44
CPC分类号： G11C29/38 , G11C29/44 , G11C2029/3202
摘要： A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.

10. 发明授权

US09620179B2 Sense amplifier and methods thereof for single ended line sensing 有权
公开(公告)号：US09620179B2
公开(公告)日：2017-04-11
申请号：US14934021
申请日：2015-11-05
申请人： Invecas, Inc.
发明人： John Edward Barth, Jr.
IPC分类号： G11C7/06 , G11C8/08 , G11C7/08 , G11C15/04
CPC分类号： G11C7/067 , G11C7/08 , G11C15/04
摘要： A sense amplifier for sensing a line of a semiconductor device comprises a p-channel pull-up transistor for charging the line, an inverter, and a pull-up controller. The p-channel pull-up transistor and the inverter are coupled to the line. The inverter inverts a line voltage of the line. The pull-up controller is coupled to the gate of the p-channel pull-up transistor and operates the p-channel pull-up transistor as a function of the inverted line voltage.

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