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1. 发明授权

US09881965B2 Back-side image sensor 有权
公开(公告)号：US09881965B2
公开(公告)日：2018-01-30
申请号：US12892372
申请日：2010-09-28
申请人： Jérôme Vaillant
发明人： Jérôme Vaillant
IPC分类号： H01L31/0232 , H01L27/146
CPC分类号： H01L27/14645 , H01L27/1464
摘要： A color back-side illuminated image sensor including, on the side of the thin semiconductor layer opposite to the illuminated surface, periodic thickness unevennesses forming an optic network having characteristics which make it capable of reflecting a given wavelength chosen within the range of the wavelengths of an illuminating incident beam.

2. 发明授权

US09704967B2 Heterojunction bipolar transistor 有权
公开(公告)号：US09704967B2
公开(公告)日：2017-07-11
申请号：US14853719
申请日：2015-09-14
申请人： STMicroelectronics S.A.
发明人： Pascal Chevalier , Didier Celi , Jean-Pierre Blanc , Alain Chantre
IPC分类号： H01L29/66 , H01L21/82 , H01L29/737 , H01L21/8249 , H01L27/06
CPC分类号： H01L29/66242 , H01L21/8249 , H01L27/0623 , H01L29/66325 , H01L29/737 , H01L29/7378
摘要： The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches, and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

3. 发明授权

US09582675B2 Protection of memory areas 有权
标题翻译：保护记忆区
公开(公告)号：US09582675B2
公开(公告)日：2017-02-28
申请号：US14871873
申请日：2015-09-30
申请人： STMICROELECTRONICS S.A.
发明人： Albert Martinez , William Orlando
IPC分类号： G06F21/62 , G06F12/14 , G06F21/52 , G06F21/79 , G06F21/60
CPC分类号： G06F21/62 , G06F12/1408 , G06F12/1483 , G06F21/52 , G06F21/602 , G06F21/79 , G06F2212/1052 , G06F2221/033 , G06F2221/2105
摘要： A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.
摘要翻译：一种用于将包含在至少第一存储器中的程序加载到执行单元可访问的第二存储器中的方法，其中程序处于第一存储器中的加密形式，用于控制对第二存储器的访问的电路是由程序初始化数据，程序的指令，以及至少初始化数据被解密以在电路配置之后被传送到第二存储器中。

4. 发明授权

US09224708B2 Method for manufacturing a conducting contact on a conducting element 有权
标题翻译：在导电元件上制造导电接触的方法
公开(公告)号：US09224708B2
公开(公告)日：2015-12-29
申请号：US14339630
申请日：2014-07-24
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMICROELECTRONICS SA
发明人： Jean-Philippe Colonna , Perceval Coudrain
IPC分类号： H01L23/48 , H01L23/00 , H01L21/768 , H01L21/306 , H01L21/48 , H01L23/31 , H01L21/683
CPC分类号： H01L24/19 , H01L21/30604 , H01L21/4853 , H01L21/6836 , H01L21/7685 , H01L21/76898 , H01L23/3171 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/20 , H01L2224/11462 , H01L2224/11472 , H01L2224/13009 , H01L2224/13076 , H01L2224/1308 , H01L2224/13082 , H01L2224/13084 , H01L2224/13144 , H01L2224/13147 , H01L2224/13166 , H01L2224/13171 , H01L2224/13181 , H01L2224/13186 , H01L2224/1356 , H01L2224/13565 , H01L2224/13582 , H01L2224/13583 , H01L2224/13644 , H01L2224/13647 , H01L2224/13666 , H01L2224/13671 , H01L2224/13681 , H01L2224/13686 , H01L2224/14181 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01073 , H01L2924/01079 , H01L2924/15788 , H01L2924/00014 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/00012 , H01L2924/00
摘要： The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.
摘要翻译：本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫在所述导电元件上。

5. 发明授权

US09077282B2 Device of variable capacitance 有权
标题翻译：可变电容器件
公开(公告)号：US09077282B2
公开(公告)日：2015-07-07
申请号：US13745634
申请日：2013-01-18
申请人： STMicroelectronics S.A. , International Business Machines Corporation
发明人： Yvan Morandini , Romain Debrouke
IPC分类号： H03B5/12 , H03B28/00 , H03H11/00 , H03J3/20
CPC分类号： H03B28/00 , H03B5/12 , H03B5/1212 , H03B5/1228 , H03B5/1253 , H03B5/1265 , H03H11/00 , H03J3/20
摘要： A variable capacitance device including: first and second transistors coupled in series by their main current nodes between first and second nodes of the device, a control node of the first transistor being adapted to receive a first control signal, and a control node of the second transistor being adapted to receive a second control signal; and control circuitry adapted to generate the first and second control signals from a selection signal.
摘要翻译：一种可变电容器件，包括：第一和第二晶体管，其由器件的第一和第二节点之间的主要电流节点串联连接，第一晶体管的控制节点适于接收第一控制信号，第二晶体管的控制节点晶体管适于接收第二控制信号; 以及适于从选择信号产生第一和第二控制信号的控制电路。

6. 发明授权

US09019666B2 Electronic device, in particular for protection against electrostatic discharges, and method for protecting a component against electrostatic discharges 有权
标题翻译：电子装置，特别是用于防止静电放电，以及用于保护部件免受静电放电的方法
公开(公告)号：US09019666B2
公开(公告)日：2015-04-28
申请号：US13574497
申请日：2011-01-20
申请人： Johan Bourgeat , Christophe Entringer , Philippe Galy , Jean Jimenez
发明人： Johan Bourgeat , Christophe Entringer , Philippe Galy , Jean Jimenez
IPC分类号： H02H9/00 , H02H9/04 , H01L23/60 , H01L27/02
CPC分类号： H02H9/044 , H01L23/60 , H01L27/0274 , H01L27/0277 , H01L2924/0002 , H01L2924/00
摘要： The electronic device includes a first (BP) and a second (BN) terminal and electronic means coupled between said two terminals; the electronic means include at least one block (BLC) comprising an MOS transistor (TR) including a parasitic bipolar transistor, the MOS transistor having the drain (D) thereof coupled to the first terminal (BP), the source (S) thereof coupled to the second terminal (BN) and being additionally configured, in the event of a current pulse (IMP) between the two terminals, to operate in a hybrid mode including MOS operation in a subthreshold mode and operation of the parasitic bipolar transistor. The device can comprise two blocks (BLC1, BLC2) connected symmetrically between the two terminals (BP, BN) with a triac (TRC) the trigger of which is connected to the common terminal (BC) of the two blocks.
摘要翻译：电子设备包括耦合在所述两个终端之间的第一（BP）和第二（BN）终端和电子设备; 所述电子装置包括至少一个包括包括寄生双极晶体管的MOS晶体管（TR）的块（BLC），所述MOS晶体管的漏极（D）耦合到所述第一端子（BP），所述源极（S）耦合（BN）并且在两个端子之间的电流脉冲（IMP）的情况下另外配置为以包括亚阈值模式中的MOS操作和寄生双极晶体管的操作的混合模式操作。该装置可以包括两个端子（BP，BN）之间对称地连接有三端双向可控硅开关元件（TRC）的两个模块（BLC1，BLC2），触发器连接到两个模块的公共端子（BC）。

7. 发明授权

US08907284B2 Terahertz imager with global reset 有权
标题翻译：太赫兹成像仪全局复位
公开(公告)号：US08907284B2
公开(公告)日：2014-12-09
申请号：US13692691
申请日：2012-12-03
申请人： STMicroelectronics S.A.
发明人： Hani Sherry , Andreia Cathelin , Ullrich Pfeiffer , Janusz Grzyb , Richard Al Hadi
IPC分类号： G01J5/00 , G01J5/02 , G01J5/34 , H03K3/03 , G05F3/26
CPC分类号： G01J5/34 , G05F3/26 , H01Q1/2283 , H01Q7/00 , H03K3/0315
摘要： A pixel circuit may include a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna. The antenna may be configured to be sensitive to terahertz radiation. The pixel circuit may also include a capacitor coupled to an intermediate node between the first and second transistors, and control circuitry coupled to control nodes of the first and second transistors. The control circuitry may be configured for selectively applying to the control nodes a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit, and/or a reset voltage for resetting a voltage stored by the capacitor.
摘要翻译：像素电路可以包括具有串联耦合在天线的差分输出节点之间的第一和第二晶体管的检测电路。天线可以被配置为对太赫兹辐射敏感。像素电路还可以包括耦合到第一和第二晶体管之间的中间节点的电容器，以及耦合到第一和第二晶体管的控制节点的控制电路。控制电路可以被配置为在像素电路的检测阶段期间选择性地向控制节点施加用于偏置第一和第二晶体管的控制节点的栅极偏置电压，和/或用于复位由像素电路存储的电压的复位电压电容器。

8. 发明授权

US08822332B2 Method for forming gate, source, and drain contacts on a MOS transistor 有权
标题翻译：在MOS晶体管上形成栅极，源极和漏极接触的方法
公开(公告)号：US08822332B2
公开(公告)日：2014-09-02
申请号：US13871884
申请日：2013-04-26
申请人： STMicroelectronics S.A. , Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Heimanu Niebojewski , Yves Morand , Cyrille Le Royer , Fabrice Nemouchi
IPC分类号： H01L21/311 , H01L21/28 , H01L29/66 , H01L21/768
CPC分类号： H01L29/66477 , H01L21/28247 , H01L21/76897 , H01L21/823425 , H01L21/823443 , H01L21/823475 , H01L21/84 , H01L29/66545 , H01L29/66606
摘要： A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.
摘要翻译：一种用于在MOS晶体管上形成栅极，源极和漏极接触的方法，其具有包括被金属栅极硅化物覆盖的多晶硅的绝缘栅极，该栅极由至少一个由第一绝缘材料制成的隔离物包围，该方法包括以下步骤： a）用第二绝缘材料覆盖结构并使第二绝缘材料平整以到达栅极硅化物; b）氧化栅极，使得栅极硅化物掩埋并覆盖氧化硅; c）选择性地去除所述第二绝缘材料; 以及d）用第一导电材料覆盖所述结构，并且将所述第一导电材料一直调整到所述隔离物顶部的较低水平。

9. 发明申请

US20140235186A1 RADIO FREQUENCY SIGNAL TRANSMISSION METHOD AND DEVICE 有权
标题翻译：无线电频率信号传输方法和装置
公开(公告)号：US20140235186A1
公开(公告)日：2014-08-21
申请号：US14177358
申请日：2014-02-11
申请人： Institut Polytechnique de Bordeaux , STMicroelectronics S.A.
发明人： Didier Belot , Yann Deval , Francois Rivet
IPC分类号： H04B1/00
CPC分类号： H04B1/0021 , H04B1/0014 , H04B1/406 , H04B2001/0491 , H04L27/2639 , H04L27/2642
摘要： A method for generating a radio frequency signal, wherein a signal to be transmitted is decomposed into a weighted sum of periodic basic signals of different frequencies.
摘要翻译：一种用于产生射频信号的方法，其中待传输的信号被分解成不同频率的周期性基本信号的加权和。

10. 发明授权

US08799623B2 Hierarchical reconfigurable computer architecture 有权
标题翻译：分层可重构计算机体系结构
公开(公告)号：US08799623B2
公开(公告)日：2014-08-05
申请号：US12086971
申请日：2006-12-22
申请人： Joël Cambonie
发明人： Joël Cambonie
IPC分类号： G06F15/80 , G06F15/78 , G06F15/173 , G06F9/38 , G06F13/368
CPC分类号： G06F15/7867 , G06F9/3885 , G06F13/368 , G06F15/173 , G06F15/17381 , G06F15/803
摘要： A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.
摘要翻译：一种具有N个级别的可重构分层计算机架构，其中N是大于1的整数值，其中所述N个级别包括第一级，包括第一计算块，所述第一级包括第一数据输入，第一数据输出和多个计算节点，第一连接机构，每个计算节点包括输入端口，功能单元和输出端口，所述第一连接机构能够将每个输出端口连接到彼此的计算节点的输入端口; 以及第二级，包括第二计算块，包括第二数据输入，第二数据输出和通过第二连接装置互连的多个第一计算块，用于选择性地连接每个第一计算块和第二计算块的第一数据输出数据输入到每个第一数据输入端，并且用于选择性地将每个第一数据输出连接到第二数据输出。

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