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1. 发明公开

US20230382724A1 DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE 审中-公开
公开(公告)号：US20230382724A1
公开(公告)日：2023-11-30
申请号：US17825225
申请日：2022-05-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wen-Chuan Tai , Hsiang-Fu Chen , Chia-Ming Hung , I-Hsuan Chiu , Fan Hu
IPC分类号： B81C1/00 , B81B3/00
CPC分类号： B81C1/00801 , B81B3/0051 , B81B2203/0127 , B81C2201/053
摘要： Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.

2. 发明授权

US09950921B2 MEMS structure with improved shielding and method 有权
公开(公告)号：US09950921B2
公开(公告)日：2018-04-24
申请号：US14930642
申请日：2015-11-02
申请人： mCube Inc.
发明人： Te-Hsi “Terrence” Lee , Sudheer S. Sridharamurthy , Shingo Yoneoka , Wenhua Zhang
IPC分类号： B81B7/00 , B81C1/00 , B81B3/00
CPC分类号： B81B7/0022 , B81B3/0086 , B81B2203/0118 , B81B2203/0307 , B81B2207/11 , B81C1/00246 , B81C1/0038 , B81C1/00531 , B81C1/00801 , B81C2201/053
摘要： An integrated circuit includes a substrate member having a surface region and a CMOS IC layer overlying the surface region. The CMOS IC layer has at least one CMOS device. The integrated circuit also includes a bottom isolation layer overlying the CMOS IC layer, a shielding layer overlying a portion of the bottom isolation layer, and a top isolation layer overlying a portion of the bottom isolation layer. The bottom isolation layer includes an isolation region between the top isolation layer and the shielding layer. The integrated circuit also has a MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer. The MEMS layer includes at least one MEMS structure having at least one movable structure and at least one anchored structure. The at least one anchored structure is coupled to a portion of the top isolation layer, and the at least one movable structure overlies the shielding layer.

3. 发明申请

US20170355598A1 STRUCTURE TO REDUCE BACKSIDE SILICON DAMAGE 审中-公开
公开(公告)号：US20170355598A1
公开(公告)日：2017-12-14
申请号：US15671647
申请日：2017-08-08
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Yen Chou , Chih-Jen Chan , Chia-Shiung Tsai , Ru-Liang Lee , Yuan-Chih Hsieh
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00595 , B81B7/007 , B81B2201/0235 , B81B2201/0242 , B81B2201/0264 , B81B2201/0271 , B81B2201/0292 , B81B2203/0109 , B81C1/00357 , B81C1/00801 , B81C2201/0132
摘要： An integrated circuit (IC) device is provided. The IC device includes a first die including a first substrate and a second die including a second substrate. A plasma-reflecting layer is included on an upper surface of the first die. The plasma-reflecting layer is configured to reflect a plasma therefrom. The second substrate is bonded to the first die so as to form a cavity, wherein a lower surface of the cavity is lined by the plasma-reflecting layer. A dielectric protection layer is present on a lower surface of the second die and lines the upper surface of the cavity. A material of the second substrate has a first etch rate for the plasma and a material of the dielectric protection layer has a second etch rate for the plasma. The second etch rate is less than the first etch rate.

4. 发明申请

US20170267516A1 MICROELECTROMECHANICAL SYSTEMS (MEMS) STRUCTURE TO PREVENT STICTION AFTER A WET CLEANING PROCESS 审中-公开
公开(公告)号：US20170267516A1
公开(公告)日：2017-09-21
申请号：US15615238
申请日：2017-06-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Yen Chou
IPC分类号： B81B3/00 , B81C1/00
CPC分类号： B81B3/001 , B81B2203/0163 , B81B2207/012 , B81C1/00801 , B81C1/00952 , B81C2201/013 , B81C2201/014 , B81C2203/0792
摘要： A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

5. 发明申请

US20170247246A1 MEMS COMPONENT 有权
公开(公告)号：US20170247246A1
公开(公告)日：2017-08-31
申请号：US15506068
申请日：2015-06-23
申请人： Robert Bosch GmbH
发明人： Christoph Schelling , Benedikt Stein , Michael Stumber
IPC分类号： B81B3/00
CPC分类号： B81B3/0086 , B81B2201/01 , B81B2201/0228 , B81B2201/0257 , B81B2201/0264 , B81B2203/0127 , B81B2203/0136 , B81C1/00801
摘要： A layer material which is particularly suitable for the realization of self-supporting structural elements having an electrode in the layer structure of a MEMS component. The self-supporting structural element is at least partially made up of a silicon carbonitride (Si1-x-yCxNy)-based layer.

6. 发明申请

US20170174505A1 INFRARED SENSOR DESIGN USING AN EPOXY FILM AS AN INFRARED ABSORPTION LAYER 审中-公开
公开(公告)号：US20170174505A1
公开(公告)日：2017-06-22
申请号：US15447932
申请日：2017-03-02
申请人： Texas Instruments Incorporated
发明人： Ricky Alan JACKSON , Walter Baker MEINEL , Kalin Valeriev LAZAROV , Brian E. GOODLIN
IPC分类号： B81B7/00 , B81C1/00 , H01L27/144
CPC分类号： B81B7/0019 , B81B2201/014 , B81C1/0038 , B81C1/00523 , B81C1/0069 , B81C1/00801 , H01L27/144
摘要： A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal.

7. 发明授权

US09676606B2 Microelectromechanical systems (MEMS) structure to prevent stiction after a wet cleaning process 有权
公开(公告)号：US09676606B2
公开(公告)日：2017-06-13
申请号：US14699070
申请日：2015-04-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chung-Yen Chou
IPC分类号： H01L21/768 , B81B3/00 , B81C1/00
CPC分类号： B81B3/001 , B81B2203/0163 , B81B2207/012 , B81C1/00801 , B81C1/00952 , B81C2201/013 , B81C2201/014 , B81C2203/0792
摘要： A method for manufacturing a microelectromechanical systems (MEMS) structure with sacrificial supports to prevent stiction is provided. A first etch is performed into an upper surface of a carrier substrate to form a sacrificial support in a cavity. A thermal oxidation process is performed to oxidize the sacrificial support, and to form an oxide layer lining the upper surface and including the oxidized sacrificial support. A MEMS substrate is bonded to the carrier substrate over the carrier substrate and through the oxide layer. A second etch is performed into the MEMS substrate to form a movable mass overlying the cavity and supported by the oxidized sacrificial support. A third etch is performed into the oxide layer to laterally etch the oxidized sacrificial support and to remove the oxidized sacrificial support. A MEMS structure with anti-stiction bumps is also provided.

8. 发明申请

US20170066648A1 CMOS-MEMS INTEGRATED DEVICE WITH SELECTIVE BOND PAD PROTECTION 审中-公开
标题翻译：具有选择性焊盘保护的CMOS-MEMS集成器件
公开(公告)号：US20170066648A1
公开(公告)日：2017-03-09
申请号：US15356916
申请日：2016-11-21
申请人： INVENSENSE, INC.
发明人： Daesung LEE
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00801 , B81B7/0025 , B81B2207/07 , B81C2201/053 , B81C2203/0785
摘要： A method and system for preparing a semiconductor wafer are disclosed. In a first aspect, the method comprises providing a passivation layer over a patterned top metal on the semiconductor wafer, etching the passivation layer to open a bond pad in the semiconductor wafer using a first mask, depositing a protection layer on the semiconductor wafer, patterning the protective layer using a second mask, and etching the passivation layer to open other electrodes in the semiconductor wafer using a third mask. The system comprises a MEMS device that further comprises a first substrate and a second substrate bonded to the first substrate, wherein the second substrate is prepared by the aforementioned steps of the method.
摘要翻译：公开了一种用于制备半导体晶片的方法和系统。在第一方面，该方法包括在半导体晶片上的图案化顶部金属上提供钝化层，蚀刻钝化层以使用第一掩模打开半导体晶片中的接合焊盘，在半导体晶片上沉积保护层，图案化使用第二掩模的保护层，并且使用第三掩模蚀刻钝化层以打开半导体晶片中的其它电极。该系统包括MEMS器件，其还包括第一基底和与第一基底结合的第二基底，其中第二基底是通过上述方法的步骤制备的。

9. 发明授权

US09573805B2 MEMS pressure sensor and method of manufacturing the same 有权
标题翻译： MEMS压力传感器及其制造方法
公开(公告)号：US09573805B2
公开(公告)日：2017-02-21
申请号：US14713946
申请日：2015-05-15
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Guangcai Fu , Haiyong Ni
IPC分类号： G01L9/00 , B81C1/00 , B81B7/00 , B81B3/00
CPC分类号： B81C1/00531 , B81B3/007 , B81B7/0058 , B81B2201/0264 , B81C1/00801 , B81C1/00849 , G01L9/0073
摘要： A method of manufacturing a pressure sensor is provided. The method includes: providing a substrate, wherein a bottom electrode and a pressure sensing film are disposed on the substrate; forming an etch stop assembly on the pressure sensing film at a location corresponding to a pressure trench; forming a cover layer on the substrate covering the etch stop assembly and the pressure sensing film; forming a mask layer on the cover layer, wherein an opening of the mask layer is formed above the etch stop assembly and exposes a portion of the cover layer at the location corresponding to the pressure trench; etching the cover layer using the mask layer so as to form the pressure trench in the cover layer; removing the etch stop assembly at a bottom of the pressure trench; and removing the mask layer.
摘要翻译：提供一种制造压力传感器的方法。该方法包括：提供衬底，其中底部电极和压力感测膜设置在衬底上; 在对应于压力沟槽的位置处在所述压力感测膜上形成蚀刻停止组件; 在覆盖所述蚀刻停止组件和所述压力感测膜的所述衬底上形成覆盖层; 在所述覆盖层上形成掩模层，其中所述掩模层的开口形成在所述蚀刻停止组件上方，并且在对应于所述压力沟槽的位置处暴露所述覆盖层的一部分; 使用掩模层蚀刻覆盖层，以在覆盖层中形成压力沟槽; 在所述压力沟槽的底部移除所述蚀刻停止组件; 并去除掩模层。

10. 发明申请

US20170029272A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20170029272A1
公开(公告)日：2017-02-02
申请号：US15222006
申请日：2016-07-28
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： PENG REN
IPC分类号： B81C1/00 , H01L23/00 , H01L21/67 , H01L21/687 , H01L23/48 , H01L21/768
CPC分类号： B81C1/00801 , B81C2201/0154 , B81C2201/05 , B81C2203/0778 , H01L21/67063 , H01L21/6715 , H01L21/687 , H01L21/76861 , H01L21/76873 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/11 , H01L24/13 , H01L2224/02317 , H01L2224/02372 , H01L2224/02381 , H01L2224/13024
摘要： A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer.
摘要翻译：一种制造半导体结构的方法包括：提供具有第一表面和第二表面的基底，其中在所述基底的第一表面上形成至少一个焊盘。该方法还包括形成至少一个通孔以通过从第二表面蚀刻衬底来暴露每个焊盘，形成晶种层以覆盖衬底的第二表面和每个通孔的侧壁和底表面，然后形成再分布金属层在形成在每个通孔的侧壁和底表面上的种子层的一部分上，以及围绕每个通孔的基板的第二表面。该方法还包括交替地执行预润湿处理和化学蚀刻工艺以完全去除未被再分布金属层覆盖的种子层的部分。

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