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    • 9. 发明授权
    • Method for producing a control signal which indicates a frequency error
    • 用于产生指示频率误差的控制信号的方法
    • US07095254B2
    • 2006-08-22
    • US10836633
    • 2004-04-29
    • Karl Schrodinger
    • Karl Schrodinger
    • H03D13/00
    • G01R23/005H03K5/26H03L7/087H03L7/095H04L7/033H04L2027/0073
    • A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies of a useful signal and the frequency of a reference signal exceeds a prescribed error limit value, where the useful signal and the reference signal are used to produce a pulsed signal whose pulse length is proportional to the frequency difference between the useful signal and the reference signal. The pulse length is then compared with a prescribed maximum pulse length, and the control signal is produced if the pulse length exceeds the prescribed maximum pulse length.
    • 如果频率在有用信号和参考信号之间彼此太大差异太大,则提供形成控制信号的非常简单的方法。 产生控制信号,其指示有用信号的频率与参考信号的频率之间的频率误差超过规定的误差极限值,其中使用有用信号和参考信号产生脉冲信号,脉冲信号 与有用信号和参考信号之间的频率差成比例。 然后将脉冲长度与规定的最大脉冲长度进行比较,并且如果脉冲长度超过规定的最大脉冲长度,则产生控制信号。
    • 10. 发明申请
    • Clock frequency detect with programmable jitter tolerance
    • 具有可编程抖动容限的时钟频率检测
    • US20060114032A1
    • 2006-06-01
    • US11000439
    • 2004-11-30
    • Charles GeerRobert Shearer
    • Charles GeerRobert Shearer
    • H03D13/00
    • G01R23/005H03D13/00
    • An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized with a first bit pattern and a second bit pattern, respectively. In a second, normal, mode, the first clock is coupled to the first register and the second clock is coupled to the second register. A compare unit observes the bit patterns of the first and second registers and reports when one or more predetermined relationships between the first clock and the second clock occur.
    • 公开了用于可编程确定电子系统中第一时钟和第二时钟的频率,相位和抖动关系的装置和方法。 首先,初始化,模式,第一寄存器和第二寄存器分别以第一位模式和第二位模式初始化。 在第二正常模式中,第一时钟耦合到第一寄存器,第二时钟耦合到第二寄存器。 当第一时钟和第二时钟之间的一个或多个预定关系发生时,比较单元观察第一和第二寄存器的位模式并报告。