专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09229853B2 Method and system for data de-duplication 有权
标题翻译：重复数据删除的方法和系统
公开(公告)号：US09229853B2
公开(公告)日：2016-01-05
申请号：US13977069
申请日：2011-12-20
申请人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
发明人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
IPC分类号： G06F13/12 , G06F7/00 , G06F12/02 , G06F3/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0641 , G06F3/0679 , G06F12/0802 , G06F2212/304
摘要： An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed.
摘要翻译：装置可以包括用于存储数据的非易失性随机存取存储器和耦合到非易失性随机存取存储器的处理器。该装置还可以包括数据重复数据删除模块，其可在处理器上操作以读取输入数据的签名，将签名与非易失性随机存取存储器中的第一数据进行比较，并且当签名指示匹配到第一数据。公开和要求保护其他实施例。

2. 发明授权

US09223708B2 System, method, and computer program product for utilizing a data pointer table pre-fetcher 有权
标题翻译：用于利用数据指针表预取器的系统，方法和计算机程序产品
公开(公告)号：US09223708B2
公开(公告)日：2015-12-29
申请号：US14082030
申请日：2013-11-15
申请人： NVIDIA Corporation
发明人： PrasannaKumar Shripal Kole , Chung-Hong Lai , Rahul Jain
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0888 , G06F2212/304 , G06F2212/602
摘要： A system, method, and computer program product are provided for utilizing a data pointer table pre-fetcher. In use, an assembly of a data pointer table within a main memory is identified. Additionally, the data pointer table is pre-fetched from the main memory. Further, data is sampled from the pre-fetched data pointer table. Further still, the sampled data is stored within a data pointer table cache.
摘要翻译：提供了一种用于利用数据指针表预取器的系统，方法和计算机程序产品。在使用中，识别主存储器内的数据指针表的组合。另外，数据指针表从主存储器预取。此外，从预取的数据指针表中采样数据。此外，采样数据存储在数据指针表缓存中。

3. 发明申请

US20150269084A1 OPPORTUNISTIC CACHE INJECTION OF DATA INTO LOWER LATENCY LEVELS OF THE CACHE HIERARCHY 审中-公开
标题翻译：数据缓存中的高速缓存高速缓存的高速缓存级别
公开(公告)号：US20150269084A1
公开(公告)日：2015-09-24
申请号：US14642654
申请日：2015-03-09
申请人： Andrew J. RUSHING , Kevin M. LEPAK
发明人： Andrew J. RUSHING , Kevin M. LEPAK
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/1081 , G06F2212/1024 , G06F2212/152 , G06F2212/304 , G06F2213/2806
摘要： According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.
摘要翻译：根据一个一般方面，一种方法可以包括从被配置为执行直接存储器访问的非中央处理器设备接收在存储器地址中的存储器系统内写入数据的请求。该方法还可以包括基于存储器地址，通过存储器系统的高速缓存层来确定高速缓存标签命中是否比与相干存储器互连更接近（等待时间）到中央处理器。该方法还可以包括如果缓存层产生高速缓存标签命中，则将数据注入高速缓存层。

4. 发明申请

US20130318288A1 METHOD AND SYSTEM FOR DATA DE-DUPLICATION 有权
标题翻译：用于数据失真的方法和系统
公开(公告)号：US20130318288A1
公开(公告)日：2013-11-28
申请号：US13977069
申请日：2011-12-20
申请人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
发明人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0641 , G06F3/0679 , G06F12/0802 , G06F2212/304
摘要： An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed.
摘要翻译：装置可以包括用于存储数据的非易失性随机存取存储器和耦合到非易失性随机存取存储器的处理器。该装置还可以包括数据重复数据删除模块，其可在处理器上操作以读取输入数据的签名，将签名与非易失性随机存取存储器中的第一数据进行比较，并且当签名指示匹配第一个数据。公开和要求保护其他实施例。

5. 发明申请

US20190205264A1 MEMORY MANAGEMENT UNIT PERFORMANCE THROUGH CACHE OPTIMIZATIONS FOR PARTIALLY LINEAR PAGE TABLES OF FRAGMENTED MEMORY 审中-公开
公开(公告)号：US20190205264A1
公开(公告)日：2019-07-04
申请号：US15857062
申请日：2017-12-28
申请人： QUALCOMM INCORPORATED
发明人： FELIX VARGHESE , ZHENBIAO MA , MARTIN JACOB , KUMAR SAKET , VASANTHA KUMAR BANDUR PUTTAPPA , SUJEET KUMAR
IPC分类号： G06F12/1081 , G06F12/1045 , G06F12/1027 , G06F12/1009 , G06F12/0895 , G06F12/0864
CPC分类号： G06F12/1081 , G06F12/0864 , G06F12/0895 , G06F12/1009 , G06F12/1027 , G06F12/1054 , G06F12/1063 , G06F2212/1024 , G06F2212/171 , G06F2212/304 , G06F2212/6082 , G06F2212/65 , G06F2212/68
摘要： A MMU may read page descriptors (using virtual addresses as an index) in a burst mode from page tables in a system memory. The page descriptors may include intermediate physical addresses (“IPAs”, in stage 1) and corresponding physical addresses (“PAs”, in stage 2). The virtual address in conjunction with page table base address register is used to index page descriptors into main memory. The MMU may identify a first group of contiguous IPAs beginning at a base IPA and a second group of contiguous IPAs beginning at an offset from the base IPA. The first and second groups may be separated by at least one IPA not contiguous with either the first or second group. The MMU may read a first PA from the page tables that corresponds to the base IPA. The MMU may store an entry in a buffer that includes the PA and a first linearity tag.

6. 发明授权

US09496009B2 Memory with bank-conflict-resolution (BCR) module including cache 有权
标题翻译：具有银行冲突解决（BCR）模块的内存包括缓存
公开(公告)号：US09496009B2
公开(公告)日：2016-11-15
申请号：US13841025
申请日：2013-03-15
申请人： MoSys, Inc.
发明人： Dipak Sikdar , Michael J. Miller , Jay Patel
IPC分类号： G11C7/10 , G06F12/08 , G11C8/12 , G11C8/18 , G11C11/417
CPC分类号： G11C7/1072 , G06F12/0802 , G06F2212/304 , G11C7/1039 , G11C8/12 , G11C8/18 , G11C11/417 , G11C2207/2209 , G11C2207/2245
摘要： A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
摘要翻译：存储器件包括存储器单元块和高速缓存。存储器单元块是具有多个端口的随机存取存储器。存储器单元块被分割成仅具有单个端口的子单元。高速缓存耦合到适于处理对存储器单元的相同子单元的多个访问的存储器单元块而不产生冲突，使得存储器看起来是对所述多个访问的随机存取存储器。还提供了一种操作存储器的方法，以及具有包含缓存的存储体冲突解决（BCR）模块的存储器。

7. 发明授权

US09298634B2 Client spatial locality through the use of virtual request trackers 有权
标题翻译：客户端空间位置通过使用虚拟请求跟踪器
公开(公告)号：US09298634B2
公开(公告)日：2016-03-29
申请号：US14198494
申请日：2014-03-05
申请人： Gregory Recupero
发明人： Gregory Recupero
IPC分类号： G06F3/00 , G06F13/28 , G06F5/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F2212/1041 , G06F2212/304 , G06F2212/6022 , G06F2212/6026 , G06F2217/08 , Y02D10/13
摘要： A memory request optimizer includes a memory tracker for receiving a read request from client devices and for determining whether the request address matches any of the virtual request trackers. If the request address does not match any virtual request tracker, an allocation logic allocates a next available virtual request tracker to track the request address. When the request address matches a virtual request tracker, a prefetch logic increments a current tracker match count for the virtual request tracker and determines whether a linear history of tracker match counts indicates a prefetch of a next request data is appropriate based on one or more predetermined criteria. If the linear history indicates the prefetch is appropriate, the prefetch logic obtains the next request data at an address equal to the request address plus a preconfigured request offset from the memory sub-system and stores the next request data in a cache.
摘要翻译：存储器请求优化器包括用于从客户端设备接收读取请求并确定请求地址是否匹配任何虚拟请求跟踪器的存储器跟踪器。如果请求地址与任何虚拟请求跟踪器不匹配，则分配逻辑分配下一个可用的虚拟请求跟踪器来跟踪请求地址。当请求地址与虚拟请求跟踪器匹配时，预取逻辑增加虚拟请求跟踪器的当前跟踪器匹配计数，并且确定跟踪器的线性历史是否匹配计数指示下一个请求数据的预取是基于一个或多个预定的标准如果线性历史表示预取是适当的，则预取逻辑以等于请求地址的地址加上来自存储器子系统的预配置请求偏移量获取下一个请求数据，并将下一个请求数据存储在高速缓存中。

8. 发明申请

US20150143058A1 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR UTILIZING A DATA POINTER TABLE PRE-FETCHER 有权
标题翻译：数据指示器预充电器的系统，方法和计算机程序产品
公开(公告)号：US20150143058A1
公开(公告)日：2015-05-21
申请号：US14082030
申请日：2013-11-15
申请人： NVIDIA Corporation
发明人： PrasannaKumar Shripal Kole , Chung-Hong Lai , Rahul Jain
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F12/0888 , G06F2212/304 , G06F2212/602
摘要： A system, method, and computer program product are provided for utilizing a data pointer table pre-fetcher. In use, an assembly of a data pointer table within a main memory is identified. Additionally, the data pointer table is pre-fetched from the main memory. Further, data is sampled from the pre-fetched data pointer table. Further still, the sampled data is stored within a data pointer table cache.
摘要翻译：提供了一种用于利用数据指针表预取器的系统，方法和计算机程序产品。在使用中，识别主存储器内的数据指针表的组合。另外，数据指针表从主存储器预取。此外，从预取的数据指针表中采样数据。此外，采样数据存储在数据指针表缓存中。

9. 发明申请

US20140047175A1 IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS 审中-公开
标题翻译：在非常大的高速缓存系统中实现高效的高速缓存标签
公开(公告)号：US20140047175A1
公开(公告)日：2014-02-13
申请号：US13570778
申请日：2012-08-09
申请人： Bulent Abali , Bruce L. Beukema , James A. Marcella , Paul G. Reuland , Michael M. Tsao
发明人： Bulent Abali , Bruce L. Beukema , James A. Marcella , Paul G. Reuland , Michael M. Tsao
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0802 , G06F12/0897 , G06F12/123 , G06F2212/304
摘要： A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag cache includes a fast partial large (LX) cache directory maintained separately on chip apart from a main LX cache directory (LXDIR) stored off chip in dynamic random access memory (DRAM) with large cache data (LXDATA). The tag cache stores most frequently accessed LXDIR tags. The tag cache contains predefined information enabling access to LXDATA directly on tag cache hit with matching address and data present in the LX cache. Only on tag cache misses the LXDIR is accessed to reach LXDATA.
摘要翻译：一种用于在非常大的缓存系统中实现高速缓存目录和高效缓存标签查找的方法和电路，以及提供了主题电路所在的设计结构。标签高速缓存包括除了存储在具有大缓存数据（LXDATA）的动态随机存取存储器（DRAM）中的芯片外的主LX高速缓存目录（LXDIR）之外分开保存的快速部分大（LX）高速缓存目录。标签缓存存储最常访问的LXDIR标签。标签缓存包含预定义信息，可以直接在标签缓存命中上访问LXDATA，匹配地址和LX缓存中存在的数据。只有在标签缓存未命中时才能访问LXDIR以达到LXDATA。

10. 发明申请

US20130036260A1 INFORMATION PROCESSING APPARATUS AND CACHE METHOD 失效
标题翻译：信息处理设备和缓存方法
公开(公告)号：US20130036260A1
公开(公告)日：2013-02-07
申请号：US13418006
申请日：2012-03-12
申请人： Takehiko Kurashige
发明人： Takehiko Kurashige
IPC分类号： G06F12/08
CPC分类号： G06F12/0868 , G06F2212/304 , G06F2212/313
摘要： According to one embodiment, an information processing apparatus includes a controller and a cache module. The controller is configured to issue commands for a first storage device and a second storage device, and thereby perform data transmission. The cache module is configured to use the first storage device as a read cache of the second storage device, the cache module withholding issuance of a write command to write cache data in the first storage device to the controller, when commands issued by the controller to the first storage device exceed a preset number, until the issued commands becomes equal to or less than the preset number.
摘要翻译：根据一个实施例，信息处理设备包括控制器和高速缓存模块。控制器被配置为发出用于第一存储设备和第二存储设备的命令，从而执行数据传输。高速缓存模块被配置为将第一存储设备用作第二存储设备的读取高速缓存，当控制器发出命令时，高速缓存模块将保留发出写入命令以将第一存储设备中的高速缓存数据写入控制器第一存储设备超过预设号码，直到发出的命令变为等于或小于预设号码。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式