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1. 发明申请

US20130329553A1 TRAFFIC METERING AND SHAPING FOR NETWORK PACKETS 审中-公开
标题翻译：网络包的交通计费和形状
公开(公告)号：US20130329553A1
公开(公告)日：2013-12-12
申请号：US13838971
申请日：2013-03-15
申请人： MoSys, Inc.
发明人： Mankit Tang , Jay Patel , Michael J. Miller
IPC分类号： H04L12/815
CPC分类号： H04L47/10 , G06F9/3005 , G06F13/128 , H04L47/22
摘要： An integrated circuit device comprising, an interface configured to receive signals external to said integrated circuit device; a memory; a logic unit; and a lookup table coupled with the logic unit, wherein the lookup table is configured to govern traffic of a network.
摘要翻译：一种集成电路装置，包括：被配置为在所述集成电路装置外部接收信号的接口; 记忆一个逻辑单元; 以及与所述逻辑单元耦合的查找表，其中所述查找表被配置为管理网络的业务。

2. 发明授权

US09361196B2 Memory device with background built-in self-repair using background built-in self-testing 有权
标题翻译：内置设备背景内置自修复使用背景内置自检
公开(公告)号：US09361196B2
公开(公告)日：2016-06-07
申请号：US14320632
申请日：2014-06-30
申请人： MoSys, Inc.
发明人： Bendik Kleveland , Dipak K Sikdar , Rajesh Chopra , Jay Patel
IPC分类号： G06F11/20 , G11C29/44 , G11C29/06 , G06F11/10 , G11C29/12 , G11C29/42 , G11C29/50 , G11C29/00 , G11C29/16 , G11C29/04
CPC分类号： G06F11/2094 , G06F11/106 , G11C29/06 , G11C29/12 , G11C29/16 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/808 , G11C2029/0409
摘要： A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.
摘要翻译：具有背景内置自修复模块（BBISRM）的存储器件包括主存储器，仲裁器和用于修复被测目标存储器（TMUT）的冗余存储器。存储设备还包括背景内置自检模块（BBISTM），用于识别需要背景内置自修复（BBISR）的内存部分。 BBISRM或BBISTM可以同时运行，同时在现场操作期间，存储器件可以用于执行外部访问。 BBISR可以检测和纠正存储在TMUT中的数据中的单个数据位错误。仲裁器被配置为接收包括存储器地址的读取或写入访问存储器请求，以确定读取或写入访问存储器请求的存储器地址是否与映射到冗余存储器的选定部分的存储器地址匹配，以及读取或写入分别来自冗余存储器的选定部分的数据。

3. 发明授权

US09667546B2 Programmable partitionable counter 有权
公开(公告)号：US09667546B2
公开(公告)日：2017-05-30
申请号：US13912033
申请日：2013-06-06
申请人： MoSys Inc.
发明人： Michael Morrison , Jay Patel , Man Kit Tang
IPC分类号： H04L12/801 , H04L12/815 , G06F9/30 , G06F13/12
CPC分类号： H04L47/10 , G06F9/3005 , G06F13/128 , H04L47/22
摘要： An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.

4. 发明授权

US09496009B2 Memory with bank-conflict-resolution (BCR) module including cache 有权
标题翻译：具有银行冲突解决（BCR）模块的内存包括缓存
公开(公告)号：US09496009B2
公开(公告)日：2016-11-15
申请号：US13841025
申请日：2013-03-15
申请人： MoSys, Inc.
发明人： Dipak Sikdar , Michael J. Miller , Jay Patel
IPC分类号： G11C7/10 , G06F12/08 , G11C8/12 , G11C8/18 , G11C11/417
CPC分类号： G11C7/1072 , G06F12/0802 , G06F2212/304 , G11C7/1039 , G11C8/12 , G11C8/18 , G11C11/417 , G11C2207/2209 , G11C2207/2245
摘要： A memory device includes a block of memory cells and a cache. The block of memory cells is a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
摘要翻译：存储器件包括存储器单元块和高速缓存。存储器单元块是具有多个端口的随机存取存储器。存储器单元块被分割成仅具有单个端口的子单元。高速缓存耦合到适于处理对存储器单元的相同子单元的多个访问的存储器单元块而不产生冲突，使得存储器看起来是对所述多个访问的随机存取存储器。还提供了一种操作存储器的方法，以及具有包含缓存的存储体冲突解决（BCR）模块的存储器。

5. 发明申请

US20130332708A1 PROGRAMMABLE PARTITIONABLE COUNTER 有权
标题翻译：可编程分区计数器
公开(公告)号：US20130332708A1
公开(公告)日：2013-12-12
申请号：US13912033
申请日：2013-06-06
申请人： MoSys Inc.
发明人： Michael Morrison , Jay Patel , Man Kit Tang
IPC分类号： G06F9/30
CPC分类号： H04L47/10 , G06F9/3005 , G06F13/128 , H04L47/22
摘要： An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.
摘要翻译：一种用于接收数据包的集成电路设备。集成电路装置包括可编程分区计数器，其包括用于对多个分组进行计数的第一计数器分区和用于计数分组的字节的第二计数器分区。第一计数器分区和第二计数器分区被配置为通过来自分组处理器的单个命令递增。

6. 发明申请

US20140317460A1 MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND BUILT-IN SELF-TESTING 有权
标题翻译：具有背景技术的存储器件使用背景技术建立自我修复自检
公开(公告)号：US20140317460A1
公开(公告)日：2014-10-23
申请号：US14320632
申请日：2014-06-30
申请人： MOSYS, INC.
发明人： Bendik Kleveland , Dipak K. Sikdar , Rajesh Chopra , Jay Patel
IPC分类号： G06F11/20 , G11C29/12
CPC分类号： G06F11/2094 , G06F11/106 , G11C29/06 , G11C29/12 , G11C29/16 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/808 , G11C2029/0409
摘要： A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.
摘要翻译：具有背景内置自修复模块（BBISRM）的存储器件包括主存储器，仲裁器和用于修复被测目标存储器（TMUT）的冗余存储器。存储设备还包括背景内置自检模块（BBISTM），用于识别需要背景内置自修复（BBISR）的内存部分。 BBISRM或BBISTM可以同时运行，同时在现场操作期间，存储器件可以用于执行外部访问。 BBISR可以检测和纠正存储在TMUT中的数据中的单个数据位错误。仲裁器被配置为接收包括存储器地址的读取或写入访问存储器请求，以确定读取或写入访问存储器请求的存储器地址是否与映射到冗余存储器的选定部分的存储器地址匹配，以及读取或写入分别来自冗余存储器的选定部分的数据。

7. 发明申请

US20130332665A1 MEMORY WITH BANK-CONFLICT-RESOLUTION (BCR) MODULE INCLUDING CACHE 有权
标题翻译：具有银行冲突解决（BCR）模块的记忆，包括缓存
公开(公告)号：US20130332665A1
公开(公告)日：2013-12-12
申请号：US13841025
申请日：2013-03-15
申请人： MOSYS, INC.
发明人： Dipak Sikdar , Michael J. Miller , Jay Patel
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F12/0802 , G06F2212/304 , G11C7/1039 , G11C8/12 , G11C8/18 , G11C11/417 , G11C2207/2209 , G11C2207/2245
摘要： A memory device includes a block of memory cells and a cache. The block of memory cells is not a random access memory with multiple ports. The block of memory cells is partitioned into subunits that have only a single port. The cache is coupled to the block of memory cells adapted to handle a plurality of accesses to a same subunit of memory cells without a conflict such that the memory appears to be a random access memory to said plurality of accesses. A method of operating the memory, and a memory with bank-conflict-resolution (BCR) module including cache are also provided.
摘要翻译：存储器件包括存储器单元块和高速缓存。存储器单元块不是具有多个端口的随机存取存储器。存储器单元块被分割成仅具有单个端口的子单元。高速缓存耦合到适于处理对存储器单元的相同子单元的多个访问的存储器单元块而不产生冲突，使得存储器看起来是对所述多个访问的随机存取存储器。还提供了一种操作存储器的方法，以及具有包含缓存的存储体冲突解决（BCR）模块的存储器。

8. 发明申请

US20130329555A1 DUAL COUNTER 审中-公开
标题翻译：双计数器
公开(公告)号：US20130329555A1
公开(公告)日：2013-12-12
申请号：US13911999
申请日：2013-06-06
申请人： MoSys Inc.
发明人： Jay Patel , Michael J. Miller , Michael Morrison
IPC分类号： H04L12/801
CPC分类号： H04L47/10 , G06F9/3005 , G06F13/128 , H04L47/22
摘要： An integrated circuit device for receiving packets. The integrated circuit device includes a first counter for counting a number of the packets, and a second counter for counting bytes of the packets. The first counter and the second counter are configured to be incremented by a single command from a packet processor.
摘要翻译：一种用于接收数据包的集成电路设备。该集成电路装置包括用于对多个分组进行计数的第一计数器和用于计数分组的字节的第二计数器。第一计数器和第二计数器被配置为通过来自分组处理器的单个命令递增。

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