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1. 发明申请

US20090132628A1 Method for Performing Decimal Division 有权
标题翻译：执行十进制分割的方法
公开(公告)号：US20090132628A1
公开(公告)日：2009-05-21
申请号：US12358885
申请日：2009-01-23
申请人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers.
摘要翻译：一种用于执行小数除法的方法，包括将输入寄存器中的缩放除数和缩放的除数接收。缩放除数的倍数的子集存储在多个多个寄存器中。商数是根据缩放除数和缩放除数计算的。每个商数由流水线机构在三个时钟周期内计算。计算包括选择新的商数，并计算新的余数。计算新余数的输入包括来自一个或多个多个寄存器的数据。

2. 发明授权

US4692891A Coded decimal non-restoring divider 失效
标题翻译：编码十进制非恢复分频器
公开(公告)号：US4692891A
公开(公告)日：1987-09-08
申请号：US668842
申请日：1984-11-06
申请人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama
发明人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama
IPC分类号： G06F7/496 , G06F7/491 , G06F7/493 , G06F7/508 , G06F7/52 , G06F7/535 , G06F7/537
CPC分类号： G06F7/4917
摘要： This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division.A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively.The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.
摘要翻译：本发明采用并行执行十进制除法中的减法处理和数位移位处理以缩短小数除法所需的时间的结构。在寄存器C中将寄存器B和除数存储除数。当加法器/减法器1的减法结果为正或0时，选择器6选择寄存器B，并且在其他时间选择寄存器A. 加法器/减法器1和移位器2以相同的方式接收来自选择器6的信号，并分别执行减法处理和移位处理。这些处理的结果分别存储在寄存器B和A'中。由于可以同时启动加法器/减法器1和移位器2，所以可以缩短分频时间。

3. 发明授权

US4384341A Data processor having carry apparatus supporting a decimal divide operation 失效
标题翻译：具有支持小数除法运算的进位装置的数据处理器
公开(公告)号：US4384341A
公开(公告)日：1983-05-17
申请号：US219638
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/496 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/508 , G06F7/52 , G06F7/533
CPC分类号： G06F7/4917
摘要： A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor with the most significant decimal digit of the remainder after each subtraction pass to predict if the next subtraction pass would result in a negative remainder. If so, a quotient decimal digit is stored in a memory, the divisor is shifted one decimal digit position to the right, and a series of subtraction passes are made to develop the next quotient decimal digit.
摘要翻译：商业指令处理器通过对由除数产生的正数余数进行计数来执行十进制除法指令来开发商。设备将除数的最有意义的十进制数与每次减法通过后余数中最有效的十进制数进行比较，以预测下一个减法通过是否会导致负余数。如果是这样的话，一个商数十进制数存储在一个存储器中，除数将一个十进制数位置向右移位，并进行一系列的减法遍数来形成下一个十进制数字。

4. 发明授权

US3578961A Preconditioned divisor for expedite division by successive subtraction 失效
标题翻译：预先分配给先进的分支机构
公开(公告)号：US3578961A
公开(公告)日：1971-05-18
申请号：US3578961D
申请日：1968-03-06
申请人： HONEYWELL INC
发明人： MIU MING-TZER
IPC分类号： G06F7/491 , G06F7/52
CPC分类号： G06F7/4917
摘要： A digital divider wherein the divisor is first preconditioned to a value which renders it more easily divisible into the dividend. Once the divisor has been optimized and the value of the dividend adjusted accordingly, actual division is effected by alternately testing the high order digits of the partial remainder and subtracting multiples of the preconditioned divisor accordingly.

5. 发明授权

US3239654A Dividing computer 失效
标题翻译：分电脑
公开(公告)号：US3239654A
公开(公告)日：1966-03-08
申请号：US8790861
申请日：1961-02-08
申请人： IBM
发明人： JACKSON ROBERT C , FLORAC WILLIAM A , WINGER WAYNE D
IPC分类号： G06F7/491 , G06F7/52
CPC分类号： G06F7/4917

6. 发明授权

US2932450A Electronic calculating apparatus 失效
标题翻译：电子计算装置
公开(公告)号：US2932450A
公开(公告)日：1960-04-12
申请号：US52773855
申请日：1955-08-11
申请人： INT COMPUTERS & TABULATORS LTD
发明人： LORIN KNIGHT , ALEC TRUSSELL
IPC分类号： G06F7/491 , G06F7/52
CPC分类号： G06F7/4917

7. 发明申请

US20130318138A1 APPARATUS AND METHOD FOR PERFORMING DECIMAL DIVISION 审中-公开
标题翻译：装置和方法，用于执行十进制划分
公开(公告)号：US20130318138A1
公开(公告)日：2013-11-28
申请号：US13996336
申请日：2011-09-30
申请人： Huan Pan
发明人： Huan Pan
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/4917
摘要： A method for performing decimal division comprises: scaling a unsigned divisor D to a range; calculating multiplies of the scaled unsigned divisor D; storing multiples of the scaled unsigned divisor in a register; predicting a next single-bit quotient using a remainder Ri; and selecting a quotient using the reminder determining if a first number S1 of a remainder of a scaled unsigned dividend B is equal to or greater than 6; calculating B−5D; and storing B−5D as Ri in a remainder register.
摘要翻译：执行小数除法的方法包括：将无符号除数D缩放到一个范围; 计算缩放的无符号除数D的乘法; 将缩放的无符号除数的倍数存储在寄存器中; 使用余数Ri来预测下一个单位商; 以及使用所述提醒来选择商，确定缩放的无符号红利B的剩余部分的第一数量S1是否等于或大于6; 计算B-5D; 并将B-5D作为Ri存储在余数寄存器中。

8. 发明授权

US07519649B2 System and method for performing decimal division 失效
标题翻译：用于执行小数除法的系统和方法
公开(公告)号：US07519649B2
公开(公告)日：2009-04-14
申请号：US11055221
申请日：2005-02-10
申请人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/496
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.
摘要翻译：一种用于执行小数除法的方法，包括接收缩放除数和除数并存储缩放除数的倍数的子集。将累积商初始化为等于零，将第一当前余数初始化为等于缩放后的余数，并将第二电流余数初始化为等于缩放后的除数减去缩放除数。执行以下循环，直到产生所选数量的商数。基于第一当前剩余部分的第一个数字计算估计的下一个商数。基于估计的下一个商数，将临时余量选择为第一当前余数或第二当前余数。通过从临时余数中减去一个存储的倍数来计算第一个下一个余数，其中根据第一个当前余数的第一个数字选择存储的倍数。通过从温度余量中减去另一个存储的倍数来计算第二个剩余部分，其中基于第一当前剩余部分选择存储的倍数中的另一个。基于估计的下一个商数，第一个当前余数和第一个下一个余数来计算实际商数。累积商用实际下一个商数更新。最后，将第一当前余数设置为等于第一下一个余数，并将第二当前余数设置为等于第二个下一个余数。

9. 发明授权

US4817048A Divider with quotient digit prediction 失效
标题翻译：分数与商数预测
公开(公告)号：US4817048A
公开(公告)日：1989-03-28
申请号：US895271
申请日：1986-08-11
申请人： Stephen J. Rawlinson , Quang H. Nguyen , R. Morse Wade
发明人： Stephen J. Rawlinson , Quang H. Nguyen , R. Morse Wade
IPC分类号： G06F7/49 , G06F7/491 , G06F7/52
CPC分类号： G06F7/4917 , G06F7/49
摘要： A divider, which performs division in a base other than 2, that reduces in most cases the number of cycles it takes to generate each quotient digit. This involves predicting the minimum possible quotient digit in response to leading digits of the partial remainder and of the divisor. The predicted minimum possible quotient digit times the divisor is then subtracted from the partial remainder. If the result of the subtraction is less than the divisor, the predicted least possible quotient digit is the correct quotient digit. If the result of the subtraction is greater than the divisor, the divisor is subtracted iteratively from that result until the partial remainder falls below the value of the divisor. For each subtraction, the predicted quotient digit is incremented by one, so that a correct quotient digit results at the end of the iteration.
摘要翻译：一个分频器，它在2以外的基极中进行除法，在大多数情况下减少了生成每个商数所需的周期数。这涉及到预测部分余数和除数的前导数字的最小可能商数。然后从部分余数中减去预测的最小可能商数乘数除数。如果减法的结果小于除数，则预测的最小可能商数是正确的商数。如果减法的结果大于除数，则从该结果中迭代地减去除数，直到部分余数低于除数的值。对于每个减法，预测商数增加1，从而在迭代结束时产生正确的商数。

10. 发明授权

US4546447A Division apparatus 失效
标题翻译：司仪器
公开(公告)号：US4546447A
公开(公告)日：1985-10-08
申请号：US459149
申请日：1983-01-19
申请人： Hideo Sawada
发明人： Hideo Sawada
IPC分类号： G06F7/493 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F7/4917
摘要： A division apparatus. A quotient of one digit and a remainder are determined by repeating execution of a single type processing of adding an integral multiple of a divisor and an intermediate remainder. The apparatus includes first, second and third registers for storing a dividend or the intermediate remainder, the integral multiple of a divisor and a carry resulted from a preceding operation, respectively, a selection circuit for selecting the complement of the integral multiple of the divisor when the carry is zero while selecting the integral multiple of the divisor when the carry is 0, an arithmetic circuit for performing adding operation on the output of the selection circuit and the content of the first register with the carry being served as the initial carry, and a counter for counting a number which corresponds to the integral multiple of the divisor. The result of the arithmetic operation which is executed in dependence on the value assumed by the carry is placed in the first register. The quotient is determined on the basis of the content of the counter.
摘要翻译：分割装置。通过重复执行添加除数和中间余数的整数倍的单一类型处理来确定一位数和余数的商。该装置包括用于分别存储除数或中间余数的第一，第二和第三寄存器，分别由先前操作产生的除数的整数倍和进位，用于选择除数积分倍数的补数的选择电路，当进位为0时选择除数的整数倍时，进位为零，用于对选择电路的输出执行加法运算的运算电路和作为初始进位的进位的第一寄存器的内容，以及用于对与除数的整数倍相对应的数字进行计数的计数器。根据进位所假设的值执行的算术运算结果位于第一个寄存器中。商根据计数器的内容确定。

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