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1. 发明申请

US20220237440A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
公开(公告)号：US20220237440A1
公开(公告)日：2022-07-28
申请号：US17611207
申请日：2020-05-07
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hajime KIMURA , Munehiro KOZUMA
IPC分类号： G06N3/063 , H01L27/108 , G06F7/492 , G06F7/496 , H01L29/786
摘要： A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

2. 发明授权

US10782933B2 Computer data processing method and apparatus for large number operations 有权
公开(公告)号：US10782933B2
公开(公告)日：2020-09-22
申请号：US16779073
申请日：2020-01-31
申请人： Alibaba Group Holding Limited
发明人： Yuan Zhao , Shan Yin
IPC分类号： G06F7/53 , G06F7/496 , G06F9/30 , G06F7/74 , G06F7/533
摘要： Implementations of this specification provide a method and apparatus for computer data processing for large number operations. An example method performed by a computing device includes splitting a multiplier and a multiplicand into respective four 64-bit numbers from most significant bits to least significant bits; reading the split multipliers and the split multiplicands into a register; and obtaining a multiplication processing result for the multiplier and the multiplicand by performing operations including: classifying the split multipliers and the split multiplicands into groups of data pairs, calculating multiplication results of the groups of data pairs one by one, performing accumulation on multiplication results of data pairs in each group, and storing an accumulation result corresponding to the data pairs in memory as the multiplication processing result for the multiplier and the multiplicand.

3. 发明授权

US09960883B1 Transmit/receive beamforming signal generation 有权
公开(公告)号：US09960883B1
公开(公告)日：2018-05-01
申请号：US15488434
申请日：2017-04-14
申请人： Texas Instruments Incorporated
发明人： Sudipto Chakraborty
IPC分类号： H04L1/00 , H03M13/41 , H03M13/00 , G06F7/487 , G06F7/496
CPC分类号： G06F7/496 , G06F7/4876 , H03L7/00
摘要： Transmit and/or receive beamforming signal generation includes a voltage-controlled oscillator (VCO) for generating a lower or higher master frequency output signal in accordance with a selection of a lower or higher frequency carrier frequency. A local oscillator generates local oscillator signals in quadrature in response to the maser frequency output signal. One or more mixer stages generate sidebands in response to a received information signal and the local oscillator signals in quadrature. The one or more mixer stages generate an output information signal in response to high-side injection of lower sidebands of the developed sidebands when the lower frequency carrier frequency is selected, and generate the output information signal in response to low-side injection of higher sidebands of the developed sidebands when the higher frequency carrier frequency is selected. Multi-band operation of transmit and receive arrays can be performed.

4. 发明授权

US5625753A Neural processor comprising means for normalizing data 失效
标题翻译：神经处理器包括用于归一化数据的装置
公开(公告)号：US5625753A
公开(公告)日：1997-04-29
申请号：US55431
申请日：1993-04-29
申请人： Yannick Deville
发明人： Yannick Deville
IPC分类号： G06G7/60 , G06F7/496 , G06F7/535 , G06F7/537 , G06F15/18 , G06N3/02 , G06N3/06 , G06N3/063
CPC分类号： G06N3/063
摘要： A neural processor, including neural calculation apparatus (30, NQ, RQ) which normalize an input data X with respect to another input data Y. The calculation apparatus performs a division of X by Y in order to determine a quotient Q. The calculation apparatus is trained to calculate by iteration a series of contributions .DELTA.Q.sub.i which are used to update a partial quotient QP which becomes the quotient Q at the end of calculation. Calculation can be performed on an arbitrary arithmetic base which determines the number of neurons utilized and also the accuracy of the calculation. It is also possible to utilize a partial remainder RP.
摘要翻译：一种神经处理器，包括使输入数据X相对于另一个输入数据Y进行归一化的神经计算装置（30，NQ，RQ）。计算装置对Y进行除法，以确定商Q。计算装置经过训练，通过迭代计算一系列的贡献DELTA Qi，用于更新在计算结束时成为商Q的部分商QP。可以对决定所使用的神经元数量的任意算术基础以及计算精度进行计算。也可以利用部分余数RP。

5. 发明授权

US4635220A Binary coded decimal number division apparatus 失效
标题翻译：二进制编码十进制数分割装置
公开(公告)号：US4635220A
公开(公告)日：1987-01-06
申请号：US549809
申请日：1983-11-08
申请人： Hideaki Yabe , Yoshio Oshima , Sako Ishikawa , Toru Ohtsuki , Masaharu Fukuta
发明人： Hideaki Yabe , Yoshio Oshima , Sako Ishikawa , Toru Ohtsuki , Masaharu Fukuta
IPC分类号： G06F7/491 , G06F7/493 , G06F7/496 , G06F7/52
CPC分类号： G06F7/4917
摘要： A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.
摘要翻译：二进制编码十进制数分割装置，其中以二进制编码十进制表示的商以逐个数字为基础通过使用商预测表和一组多值寄存器来确定，并且其中从商预测表在预测商正确的情况下完整使用，否则预测商减1，其中存储在商预测表中的值与冗余位一起预先修改为（0110）2至（1111）2 二进制编码十进制表示。通过使用修改的预测商的四位中的三位来选择多值寄存器，而在商确定时，从商预测表的输出值中减去用于修改的值，从而导出一个预测商的预测商数字。利用这种布置，从商预测表读出的一位数的预测商的四位中的三位可以直接用作选择相关除数多寄存器的选择信号。

6. 发明授权

US4484300A Data processor having units carry and tens carry apparatus supporting a decimal multiply operation 失效
标题翻译：具有单元的数据处理器进位和十进位装置支持十进制乘法运算
公开(公告)号：US4484300A
公开(公告)日：1984-11-20
申请号：US219810
申请日：1980-12-24
申请人： Virendra S. Negi , Steven A. Tague
发明人： Virendra S. Negi , Steven A. Tague
IPC分类号： G06F7/38 , G06F7/483 , G06F7/491 , G06F7/496 , G06F7/508 , G06F7/52 , G06F7/527
CPC分类号： G06F7/4915
摘要： A data processing system executes a decimal multiply instruction by storing the product of a multiplier decimal digit and a multiplicand decimal digit in a read only memory and storing partial product decimal digits in a register. The units product decimal digit is read from the read only memory during one cycle and added to a partial product decimal digit. A resulting units carry is stored in a units carry flip-flop. The tens product decimal digit is read from the read only memory during another cycle and added to a higher order partial product decimal digit. A resulting tens carry is stored in a tens carry flip-flop. A multiplexer selects the output of the units carry flip-flop for adding the units carry during the next units cycle in which the next units product decimal digit is added to the higher order partial product decimal digit. The multiplexer selects the output of the tens carry flip-flop for adding the tens carry during the next tens cycle in which the next tens product decimal digit is added to a next higher order partial product decimal digit.
摘要翻译：数据处理系统通过将乘数十进制数和乘数十进制数的乘积存储在只读存储器中并将部分乘积十进制数字存储在寄存器中来执行十进制乘法指令。单位产品十进制数字在一个周期内从只读存储器读取，并添加到部分乘积十进制数字。结果单位进位存储在单位进位触发器中。在另一个周期内，从只读存储器读取十位数十进制数，并将其加到较高阶部分乘积十进制数字。结果十进位存储在十进位触发器中。多路复用器在下一个单位周期内，将下一个单位乘积十进制数字加到较高阶部分乘积十进制数字中，选择输入单元的单元进位触发器来添加单位进位。多路复用器选择十位进位触发器的输出，在下一个十位周期中将下一个十位乘数十进制数字加到下一个高阶部分乘积十进制数字的十进位。

7. 发明授权

US4466077A Method and apparatus for division employing associative memory 失效
标题翻译：使用关联记忆的划分方法和装置
公开(公告)号：US4466077A
公开(公告)日：1984-08-14
申请号：US305765
申请日：1981-09-25
申请人： Robert A. Iannucci , James R. Kleinsteiber
发明人： Robert A. Iannucci , James R. Kleinsteiber
IPC分类号： G06F7/493 , G06F7/496 , G06F7/52 , G06F7/533 , G06F7/535 , G06F7/544
CPC分类号： G06F7/535 , G06F7/4917 , G06F2207/5353
摘要： A method and apparatus for the arithmetic division operation is disclosed in which a set of multiples of the divisor are stored in an associative memory in addresses which match the respective multiples. The most significant byte of the numerator is then compared to the contents of each associative entry. A flag is generated signifying that the corresponding entry is less than or equal to the most significant byte of the numerator. After the flags have been generated, the address of the last flag which is on, is selected. This provides a trial "digit out", which is used to address the true table of multiples and select a value which is subtracted from the left-digit-shifted numerator (or intermediate result). If no underflow condition results, the trial "digit out" is valid and should be stored and the next iteration started. For an underflow condition, the "digit out" is decremented and stored, the X1 multiple is added to the numerator and the next iteration is carried out. If the flag indicating X8 is on or at a value of 1, an X8 latch is set and a second pass is carried out, with the X8 latch output becoming part of the "digit out".
摘要翻译：公开了一种用于算术分割操作的方法和装置，其中除数的一组倍数存储在与各个倍数匹配的地址中的关联存储器中。然后将分子的最高有效字节与每个关联条目的内容进行比较。生成一个标志，表示对应的条目小于或等于分子的最高有效字节。标志生成后，选择最后一个标志位的地址。这提供了一个试验“数字输出”，用于解决真实的多个表，并选择从左数位移分子（或中间结果）中减去的值。如果没有下溢条件结果，试用“数字输出”是有效的，应该被存储并且下一次迭代开始。对于下溢条件，“数字输出”递减并存储，将X1倍数加到分子中，并进行下一次迭代。如果指示X8的标志为1或值为1，则X8锁存器被设置并执行第二遍，X8锁存器输出成为“数字输出”的一部分。

8. 发明授权

US11494625B2 Systems and methods for energy-efficient analog matrix multiplication for machine learning processes 有权
公开(公告)号：US11494625B2
公开(公告)日：2022-11-08
申请号：US16590272
申请日：2019-10-01
申请人： Maxim Integrated Products, Inc.
发明人： Sung Ung Kwak , Robert Michael Muchsel
IPC分类号： G06N3/063 , G06F7/496 , G06F7/501 , G06F9/30 , G06F17/16 , G06G7/16
摘要： A novel energy-efficient multiplication circuit using analog multipliers and adders reduces the distance data has to move and the number of times the data has to be moved when performing matrix multiplications in the analog domain. The multiplication circuit is tailored to bitwise multiply the innermost product of a rearranged matrix formula to output the generate a matrix multiplication result in form of a current that is then digitized for further processing.

9. 发明申请

US20210109713A1 DEVICE AND METHOD FOR EXTRACTION AND INSERTION OF BINARY WORDS 有权
公开(公告)号：US20210109713A1
公开(公告)日：2021-04-15
申请号：US17038584
申请日：2020-09-30
申请人： STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
发明人： Rene Peyrard , Fabrice Romain
IPC分类号： G06F7/76 , G06F7/494 , G06F7/496 , G06F7/72
摘要： The present disclosure relates to a device and method for processing masked binary data values, comprising extracting and inserting a first part of a first masked binary data value in a second masked binary data value, in which the first and second masked binary data values stay masked throughout all of the processing.

10. 发明授权

US07519649B2 System and method for performing decimal division 失效
标题翻译：用于执行小数除法的系统和方法
公开(公告)号：US07519649B2
公开(公告)日：2009-04-14
申请号：US11055221
申请日：2005-02-10
申请人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
发明人： Steven R. Carlough , Paulomi Kadakia , Wen H. Li , Eric M. Schwarz
IPC分类号： G06F7/496
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.
摘要翻译：一种用于执行小数除法的方法，包括接收缩放除数和除数并存储缩放除数的倍数的子集。将累积商初始化为等于零，将第一当前余数初始化为等于缩放后的余数，并将第二电流余数初始化为等于缩放后的除数减去缩放除数。执行以下循环，直到产生所选数量的商数。基于第一当前剩余部分的第一个数字计算估计的下一个商数。基于估计的下一个商数，将临时余量选择为第一当前余数或第二当前余数。通过从临时余数中减去一个存储的倍数来计算第一个下一个余数，其中根据第一个当前余数的第一个数字选择存储的倍数。通过从温度余量中减去另一个存储的倍数来计算第二个剩余部分，其中基于第一当前剩余部分选择存储的倍数中的另一个。基于估计的下一个商数，第一个当前余数和第一个下一个余数来计算实际商数。累积商用实际下一个商数更新。最后，将第一当前余数设置为等于第一下一个余数，并将第二当前余数设置为等于第二个下一个余数。

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