专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08812516B2 Determining top N or bottom N data values and positions 有权
标题翻译：确定顶部N个或底部N个数据值和位置
公开(公告)号：US08812516B2
公开(公告)日：2014-08-19
申请号：US13275351
申请日：2011-10-18
申请人： Ajay Anant Ingle , Mao Zeng
发明人： Ajay Anant Ingle , Mao Zeng
IPC分类号： G06F7/14 , G06F17/30 , G06F9/30 , G06F7/36
CPC分类号： G06F7/492 , G06F7/24 , G06F7/36 , G06F9/30 , G06F9/30021 , G06F9/30032 , G06F9/30036
摘要： A method includes executing an instruction at a processor, where executing the instruction includes comparing a data value of a plurality of data values to a first element stored at a first location of a storage device. When the data value satisfies a condition with respect to the first element, the method includes moving the first element to a second location of the storage device and inserting the data value into the first location of the storage device.
摘要翻译：一种方法包括在处理器处执行指令，其中执行指令包括将多个数据值的数据值与存储在存储设备的第一位置处的第一元素进行比较。当数据值满足关于第一元素的条件时，该方法包括将第一元素移动到存储设备的第二位置，并将数据值插入存储设备的第一位置。

2. 发明申请

US20090204658A1 DECIMAL COMPUTING APPARATUS, ELECTRONIC DEVICE CONNECTABLE DECIMAL COMPUTING APPARATUS, ARITHMETIC OPERATION APPARATUS, ARITHMETIC OPERATION CONTROL APPARATUS, AND PROGRAM-RECORDED RECORDING MEDIUM 有权
标题翻译：十进制计算装置，电子装置连接十进制计算装置，算术运算装置，算术运算控制装置和程序记录记录介质
公开(公告)号：US20090204658A1
公开(公告)日：2009-08-13
申请号：US12428288
申请日：2009-04-22
申请人： Hisashi ITO , Tetsuichi NAKAE
发明人： Hisashi ITO , Tetsuichi NAKAE
IPC分类号： G06F7/32
CPC分类号： G06F7/492 , G06F5/16 , G06F9/30014 , G06F2207/3816 , G06F2207/4911
摘要： A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a calculation-instruction memory section which stores the calculation instruction having the number of calculation digits and a type of calculation set therein, and a decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in the plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in the calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in the calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in the plurality of memory areas of the multidigit memory section digit unit by digit unit.
摘要翻译：在计算指令中设置的计算数字的数量进行多位数十进制计算的十进制计算装置包括：多位存储部，其存储比多个存储器中的规定数字部的位数大的位数区域，存储具有计算数字数量的计算指令和其中设置的计算类型的计算指令存储部分，以及执行十进制计算部分，其执行依次计算分别存储在多个数据中的对应数字单元的数值存储在计算指令存储器部分中的计算指令中设置的计算位数的数字单元，按计算指令存储部分存储的计算指令中设置的计算类型进行十进制计算，指令记忆部分并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域中。

3. 发明授权

US08805917B2 Parallel redundant decimal fused-multiply-add circuit 有权
标题翻译：并行冗余十进制融合乘法电路
公开(公告)号：US08805917B2
公开(公告)日：2014-08-12
申请号：US13177491
申请日：2011-07-06
申请人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
发明人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
IPC分类号： G06F7/48
CPC分类号： G06F7/492 , G06F7/483 , G06F7/5336 , G06F7/5443 , G06F2207/5355
摘要： A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.
摘要翻译：用于执行×b±c的浮点融合乘法（FMA）计算的电路。电路包括（i）部分乘积生成模块，其具有（a）多个发生器单元，被配置为生成具有m位二进制编码十进制（BCD）格式的被乘数的倍数，（b）被配置为生成n + 1个符号的重新编码单元数字（SD）从乘法器的和向量和进位向量设置，以及（c）多个选择单元，被配置为基于n + 1个SD集合和FMA的符号从被乘数的倍数生成部分乘积向量计算，以及（ii）进位保存加法器（CSA）树，其被配置为添加部分乘积向量和加数以生成m + n位BCD格式的结果和矢量和结果进位向量。

4. 发明授权

US07743084B2 Processing unit having multioperand decimal addition 有权
标题翻译：具有多位数加法的处理单元
公开(公告)号：US07743084B2
公开(公告)日：2010-06-22
申请号：US11014674
申请日：2004-12-16
申请人： Michael J. Schulte , Robert D. Kenney
发明人： Michael J. Schulte , Robert D. Kenney
IPC分类号： G06F7/50
CPC分类号： G06F7/492 , G06F7/4925
摘要： A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multi-operand decimal adder may perform speculative or non-speculative binary carry-save addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.
摘要翻译：描述了对多个二进制编码十进制（BCD）操作数执行加法的多操作数十进制加法器。多操作数十进制加法器使用二进制进位加法器产生中间和并携带，并输出基于中间和的十进制结果并携带。在各种配置中，多操作数十进制加法器可以执行推测或非推测的二进制进位保存加法。多位数十进制加法器达到合理的关键路径。因此，本文描述的十进制加法器和技术可能特别适用于数字密集型商业应用，例如通常需要快速处理大量十进制数据的电子表格或金融应用程序。

5. 发明申请

US20130097187A1 Determining Top N or Bottom N Data Values and Positions 有权
标题翻译：确定顶部N或底部N数据值和位置
公开(公告)号：US20130097187A1
公开(公告)日：2013-04-18
申请号：US13275351
申请日：2011-10-18
申请人： Ajay Anant Ingle , Mao Zeng
发明人： Ajay Anant Ingle , Mao Zeng
IPC分类号： G06F17/30
CPC分类号： G06F7/492 , G06F7/24 , G06F7/36 , G06F9/30 , G06F9/30021 , G06F9/30032 , G06F9/30036
摘要： A method includes executing an instruction at a processor, where executing the instruction includes comparing a data value of a plurality of data values to a first element stored at a first location of a storage device. When the data value satisfies a condition with respect to the first element, the method includes moving the first element to a second location of the storage device and inserting the data value into the first location of the storage device.
摘要翻译：一种方法包括在处理器处执行指令，其中执行指令包括将多个数据值的数据值与存储在存储设备的第一位置处的第一元素进行比较。当数据值满足关于第一元素的条件时，该方法包括将第一元素移动到存储设备的第二位置，并将数据值插入存储设备的第一位置。

6. 发明申请

US20120011187A1 PARALLEL REDUNDANT DECIMAL FUSED-MULTIPLY-ADD CIRCUIT 有权
标题翻译：并行冗余多路复用多路复用电路
公开(公告)号：US20120011187A1
公开(公告)日：2012-01-12
申请号：US13177491
申请日：2011-07-06
申请人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
发明人： Amira Mohamed , Ramy Raafat , Hossam Ali Hassan Fahmy , Tarek Eldeeb , Yasmeen Farouk , Rodina Samy , Mostafa Elkhouly
IPC分类号： G06F7/52 , G06F7/50
CPC分类号： G06F7/492 , G06F7/483 , G06F7/5336 , G06F7/5443 , G06F2207/5355
摘要： A circuit for performing a floating-point fused-multiply-add (FMA) calculation of a×b±c. The circuit includes (i) a partial product generation module having (a) a multiples generator unit configured to generate multiples of a multiplicand has m digit binary coded decimal (BCD) format, (b) a recoding unit configured to generate n+1 signed digits (SD) sets from a sum vector and a carry vector of a multiplier, and (c) a multiples selection unit configured to generate partial product vectors from the multiples of the multiplicand based on the n+1 SD sets and the sign of FMA calculation, and (ii) a carry save adder (CSA) tree configured to add the partial product vectors and an addend to generate a result sum vector and a result carry vector in a m+n digit BCD format.
摘要翻译：用于执行×b±c的浮点融合乘法（FMA）计算的电路。电路包括（i）部分乘积生成模块，其具有（a）多个发生器单元，被配置为生成具有m位二进制编码十进制（BCD）格式的被乘数的倍数，（b）被配置为生成n + 1个符号的重新编码单元数字（SD）从乘法器的和向量和进位向量设置，以及（c）多个选择单元，被配置为基于n + 1个SD集合和FMA的符号从被乘数的倍数生成部分乘积向量计算，以及（ii）进位保存加法器（CSA）树，其被配置为添加部分乘积向量和加数以生成m + n位BCD格式的结果和矢量和结果进位向量。

7. 发明授权

US08316067B2 Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium 有权
标题翻译：十进制计算装置，电子装置连接十进制计算装置，算术运算装置，算术运算控制装置以及程序记录记录介质
公开(公告)号：US08316067B2
公开(公告)日：2012-11-20
申请号：US12428288
申请日：2009-04-22
申请人： Hisashi Ito , Tetsuichi Nakae
发明人： Hisashi Ito , Tetsuichi Nakae
IPC分类号： G06F3/00 , G06F7/38
CPC分类号： G06F7/492 , G06F5/16 , G06F9/30014 , G06F2207/3816 , G06F2207/4911
摘要： A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a calculation-instruction memory section which stores the calculation instruction having the number of calculation digits and a type of calculation set therein, and a decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in the plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in the calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in the calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in the plurality of memory areas of the multidigit memory section digit unit by digit unit.
摘要翻译：在计算指令中设置的计算数字的数量进行多位数十进制计算的十进制计算装置包括：多位存储部，其存储比多个存储器中的规定数字部的位数大的位数区域，存储具有计算数字数量的计算指令和其中设置的计算类型的计算指令存储部分，以及执行十进制计算部分，其执行依次计算分别存储在多个数据中的对应数字单元的数值存储在计算指令存储器部分中的计算指令中设置的计算位数的数字单元，按计算指令存储部分存储的计算指令中设置的计算类型进行十进制计算，指令记忆部分并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域中。

8. 发明授权

US07716267B2 Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium 有权
标题翻译：十进制计算装置，电子装置连接十进制计算装置，算术运算装置，算术运算控制装置以及程序记录记录介质
公开(公告)号：US07716267B2
公开(公告)日：2010-05-11
申请号：US11109888
申请日：2005-04-19
申请人： Hisashi Ito , Tetsuichi Nakae
发明人： Hisashi Ito , Tetsuichi Nakae
IPC分类号： G06F7/38 , G06F7/50
CPC分类号： G06F7/492 , G06F5/16 , G06F9/30014 , G06F2207/3816 , G06F2207/4911
摘要： Decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in calculation instruction, comprises multidigit memory section capable of storing values with greater numbers of digits than the number of digits of a predetermined digit unit in plurality of memory areas; calculation-instruction memory section which stores calculation instruction having the number of calculation digits and type of calculation set therein; and decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in plurality of memory areas of multidigit memory section digit unit by digit unit.
摘要翻译：十进制计算装置，其在计算指令中设置的计算数字的数量进行多位数十进制计算，包括多位存储器部分，其能够存储具有比多个存储区域中的预定数字单元的位数更大的位数的值; 计算指令存储部，其存储具有计算数的个数和其中设定的计算类型的计算指令; 和十进制计算部分，执行十进制计算，其执行十进制计算，其顺次计算分别存储在多位存储部分的多个存储区域中的数字单位的数值，以计数指令中存储的计算指令中设置的计算数字的数量为单位的数字单位存储器部分，根据存储在计算指令存储器部分中的计算指令中设置的计算类型进行十进制计算，并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域。

9. 发明申请

US20060064455A1 Processing unit having multioperand decimal addition 有权
标题翻译：具有多位数加法的处理单元
公开(公告)号：US20060064455A1
公开(公告)日：2006-03-23
申请号：US11014674
申请日：2004-12-16
申请人： Michael Schulte , Robert Kenney
发明人： Michael Schulte , Robert Kenney
IPC分类号： G06F7/50
CPC分类号： G06F7/492 , G06F7/4925
摘要： A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multi-operand decimal adder may perform speculative or non-speculative binary carry-save addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.
摘要翻译：描述了对多个二进制编码十进制（BCD）操作数执行加法的多操作数十进制加法器。多操作数十进制加法器使用二进制进位加法器产生中间和并携带，并输出基于中间和的十进制结果并携带。在各种配置中，多操作数十进制加法器可以执行推测或非推测的二进制进位保存加法。多位数十进制加法器达到合理的关键路径。因此，本文描述的十进制加法器和技术可能特别适用于数字密集型商业应用，例如通常需要快速处理大量十进制数据的电子表格或金融应用程序。

10. 发明申请

US20060047740A1 Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium 有权
标题翻译：十进制计算装置，电子装置连接十进制计算装置，算术运算装置，算术运算控制装置以及程序记录记录介质
公开(公告)号：US20060047740A1
公开(公告)日：2006-03-02
申请号：US11109888
申请日：2005-04-19
申请人： Hisashi Ito , Tetsuichi Nakae
发明人： Hisashi Ito , Tetsuichi Nakae
IPC分类号： G06F7/52
CPC分类号： G06F7/492 , G06F5/16 , G06F9/30014 , G06F2207/3816 , G06F2207/4911
摘要： Decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in calculation instruction, comprises multidigit memory section capable of storing values with greater numbers of digits than the number of digits of a predetermined digit unit in plurality of memory areas; calculation-instruction memory section which stores calculation instruction having the number of calculation digits and type of calculation set therein; and decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in plurality of memory areas of multidigit memory section digit unit by digit unit.
摘要翻译：十进制计算装置，其在计算指令中设置的计算数字的数量进行多位数十进制计算，包括多位存储器部分，其能够存储具有比多个存储区域中的预定数字单元的位数更大的位数的值; 计算指令存储部，其存储具有计算数的个数和其中设定的计算类型的计算指令; 和十进制计算部分，执行十进制计算，其执行十进制计算，其顺次计算分别存储在多位存储部分的多个存储区域中的数字单位的数值，以计数指令中存储的计算指令中设置的计算数字的数量为单位的数字单位存储器部分，根据存储在计算指令存储器部分中的计算指令中设置的计算类型进行十进制计算，并且将计算结果顺序地写入多位存储器部分数字单元的多个存储区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式