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1. 发明申请

US20180137905A1 MEMORY CELLS AND SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MATERIALS 审中-公开
公开(公告)号：US20180137905A1
公开(公告)日：2018-05-17
申请号：US15854334
申请日：2017-12-26
申请人： Micron Technology, Inc.
发明人： Steven C. Nicholes , Ashonita A. Chavan , Matthew N. Rocklein
IPC分类号： G11C11/22 , H01L49/02 , H01L27/11507
CPC分类号： G11C11/225 , G11C11/22 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C11/5657 , G11C13/047 , G11C14/00 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/65 , H01L28/75
摘要： Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

2. 发明申请

US20170352396A1 CHARGE SHARING BETWEEN MEMORY CELL PLATES 审中-公开
公开(公告)号：US20170352396A1
公开(公告)日：2017-12-07
申请号：US15659994
申请日：2017-07-26
申请人： Micron Technology, Inc.
发明人： Eric S. Carman
IPC分类号： G11C11/22 , G11C11/56 , G11C8/08 , G11C13/04
CPC分类号： G11C11/225 , G11C8/08 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C13/047
摘要： Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

3. 发明授权

US09697881B2 Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors 有权
公开(公告)号：US09697881B2
公开(公告)日：2017-07-04
申请号：US15241550
申请日：2016-08-19
申请人： Micron Technology, Inc.
发明人： Steven C. Nicholes , Ashonita A. Chavan , Matthew N. Rocklein
IPC分类号： G11C11/22 , H01L27/11507 , G11C11/56 , H01L27/11502 , G11C14/00
CPC分类号： G11C11/225 , G11C11/22 , G11C11/221 , G11C11/2273 , G11C11/2275 , G11C11/2297 , G11C11/5657 , G11C13/047 , G11C14/00 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/56 , H01L28/65 , H01L28/75
摘要： Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

4. 发明申请

US20150357050A1 Reliability Screening of Ferroelectric Memories in Integrated Circuits 有权
标题翻译：集成电路中铁电存储器的可靠性筛选
公开(公告)号：US20150357050A1
公开(公告)日：2015-12-10
申请号：US14519894
申请日：2014-10-21
申请人： Texas Instruments Incorporated
发明人： Richard Bailey , John A. Rodriguez
IPC分类号： G11C29/50 , G11C11/22
CPC分类号： G11C29/50016 , G11C11/225
摘要： A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. A reference voltage level is determined for each integrated circuit being tested, corresponding to the read of a high polarization capacitance data state. A number of FRAM cells in the integrated circuit are programmed to that data state, and then read at an elevated temperature, with the number of failing cells compared against a pass/fail threshold to determine whether the integrated circuit is vulnerable to long-term data retention failure.
摘要翻译：包括铁电随机存取存储器（FRAM）阵列的集成电路的数据保持可靠性屏幕。对于正在测试的每个集成电路，对应于高偏振电容数据状态的读取，确定参考电压电平。集成电路中的多个FRAM单元被编程为该数据状态，然后在升高的温度读取，故障单元的数量与通过/失败阈值进行比较，以确定集成电路是否易受长期数据的影响保留失败。

5. 发明授权

US08767504B2 Activate signal generating circuit and semiconductor memory device 有权
标题翻译：激活信号发生电路和半导体存储器件
公开(公告)号：US08767504B2
公开(公告)日：2014-07-01
申请号：US13728727
申请日：2012-12-27
申请人： Fujistu Semiconductor Limited
发明人： Shoichiro Kawashima
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： H03H11/26 , G11C7/222 , G11C11/22 , G11C11/225 , H03K3/017 , H03K5/06
摘要： An activate signal generating circuit, to which a first and a second activate signals which are pulse signals are applied, and which generates an internal activate signal, has a first delay element. The internal activate signal is activated based on timings of front (active transient) edges of the first and second activate signals. When a timing of a rear (inactive transient) edge of the first activate signal is earlier than a timing of a rear edge of the second activate signal, the internal activate signal goes inactivate based on the timing of the rear edge of the first activate signal, and when the timing of the rear edge of the first activate signal is later than the timing of the rear edge of the second activate signal, the internal activate signal goes inactivate after a predetermined delay time based on a delay time of the first delay element.
摘要翻译：激活信号发生电路，施加作为脉冲信号的第一和第二激活信号，并且产生内部激活信号，具有第一延迟元件。内部激活信号基于第一和第二激活信号的前（有效瞬态）边沿的定时被激活。当第一激活信号的后（无效瞬态）边沿的定时早于第二激活信号的后沿的定时时，内部激活信号将基于第一激活信号的后沿的定时而失活并且当第一激活信号的后沿的定时晚于第二激活信号的后沿的定时时，内部激活信号在预定延迟时间之后基于第一延迟元件的延迟时间而失活。

6. 发明申请

US20140071752A1 NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES 有权
标题翻译：具有嵌入式快速读取和写入记忆的非易失性存储器系统
公开(公告)号：US20140071752A1
公开(公告)日：2014-03-13
申请号：US13967649
申请日：2013-08-15
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C16/10 , G11C7/10
CPC分类号： G06F12/10 , G06F2212/205 , G06F2212/214 , G11C7/1006 , G11C7/1084 , G11C11/02 , G11C11/225 , G11C13/0021 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C16/10
摘要： A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.
摘要翻译：使用具有随机存取易失性存储器的非易失性存储存储器的新颖结构来描述非易失性存储器系统。包括新的命令以增强内存系统的读写性能。

7. 发明申请

US20170316815A1 CHARGE SHARING BETWEEN MEMORY CELL PLATES USING A CONDUCTIVE PATH 有权
公开(公告)号：US20170316815A1
公开(公告)日：2017-11-02
申请号：US15141491
申请日：2016-04-28
申请人： Micron Technology, Inc.
发明人： Eric S. Carman
IPC分类号： G11C11/22 , G11C13/04 , G11C11/56 , G11C8/08
CPC分类号： G11C11/225 , G11C8/08 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C13/047
摘要： Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

8. 发明申请

US20160358640A1 Ferroelectric Memory Expansion for Firmware Updates 审中-公开
标题翻译：铁电内存扩展用于固件更新
公开(公告)号：US20160358640A1
公开(公告)日：2016-12-08
申请号：US15139865
申请日：2016-04-27
申请人： Texas Instruments Deutschland GmbH , Texas Instruments Incorporated
发明人： Ralf Brederlow , Oscar Miguel Guillen-Hernandez , Peter Wongeun Chung
IPC分类号： G11C11/22 , G06F9/445
CPC分类号： G06F8/65 , G11C11/221 , G11C11/225 , G11C11/2253
摘要： An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.
摘要翻译：包括用于存储固件的铁电随机存取存储器（FRAM）的集成电路以及更新该固件的方法。 FRAM被构造为在正常操作模式下选择性地作为2T2C FRAM存储器操作，并且作为更新模式中的1T1C FRAM存储器。存储的固件的更新通过将FRAM置于其更新（1T1C）模式并且将更新的代码写入多个存储器位置中的每一个处的1T1C半单元的交替行而执行，而另一个1T1C半单元其他替代行保留原始数据。在更新内容的验证之后，通过验证的更新数据覆盖其他半小区中的原始数据，并且将操作模式改变回正常（2T2C）操作模式。

9. 发明申请

US20160336069A1 Multi-level versatile memory 审中-公开
标题翻译：多层通用记忆体
公开(公告)号：US20160336069A1
公开(公告)日：2016-11-17
申请号：US15153574
申请日：2016-05-12
申请人： James Lin
发明人： James Lin
IPC分类号： G11C14/00 , G11C11/56 , G11C11/406
CPC分类号： G11C11/5657 , G06F12/0802 , G11C8/12 , G11C11/005 , G11C11/221 , G11C11/225
摘要： MLVM is a DRAM product that has the flexibility for certain performance characteristics to change based on programming characteristics made when writing the data and the ability to write multiple bits of data at the same time. At the simplest level, this means that depending on the type of operation(s) being executed, certain more favorable characteristics can be programmed into the DRAM to get benefits over the current state of the art. The most likely benefits would be in power utilization and heat.
摘要翻译： MLVM是一种DRAM产品，具有灵活性，可以根据编写数据时的编程特性以及同时写入多个数据位的能力来改变某些性能特征。在最简单的层次上，这意味着根据正在执行的操作类型，某些更有利的特性可被编程到DRAM中，以获得比当前技术水平更高的优点。最有利的是电力利用和热量。

10. 发明授权

US08817537B2 Nonvolatile memory systems with embedded fast read and write memories 有权
标题翻译：具有嵌入式快速读写存储器的非易失性存储器系统
公开(公告)号：US08817537B2
公开(公告)日：2014-08-26
申请号：US13967649
申请日：2013-08-15
申请人： G. R. Mohan Rao
发明人： G. R. Mohan Rao
IPC分类号： G11C14/00 , G11C16/06 , G11C7/00 , G11C16/10
CPC分类号： G06F12/10 , G06F2212/205 , G06F2212/214 , G11C7/1006 , G11C7/1084 , G11C11/02 , G11C11/225 , G11C13/0021 , G11C14/00 , G11C14/0018 , G11C16/06 , G11C16/10
摘要： A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.
摘要翻译：使用具有随机存取易失性存储器的非易失性存储存储器的新颖结构来描述非易失性存储器包括新的命令以增强内存系统的读写性能。

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