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1. 发明授权

US12066815B2 Recipe creation method or apparatus utilizing a series of steps according to a target recipe file for semiconductor manufacturing or substrating processing 有权
公开(公告)号：US12066815B2
公开(公告)日：2024-08-20
申请号：US17477249
申请日：2021-09-16
申请人： Kokusai Electric Corporation
发明人： Takatoshi Seki
IPC分类号： G05B99/00 , G05B19/418 , H01L21/67
CPC分类号： G05B19/41865 , H01L21/67248 , H01L21/67253 , H01L21/67276 , G05B2219/32095 , G05B2219/32097 , G05B2219/45031 , H01L21/67155
摘要： There is provided a technique that includes: displaying a recipe editing screen including at least a selection screen area that displays a parameter list for selection of parameters included in a recipe of a substrate processing apparatus, and a parameter editing screen area that edits the parameters; receiving a selection operation that selects an editing target parameter from the parameter list; displaying, on the parameter editing screen area, in an editable manner, a timing chart that is changeable at a time of each process in a series of processes included in a substrate processing process; and editing the editing target parameter by receiving an operation instruction to edit the timing chart displayed on the parameter editing screen area and changing the timing chart according to the operation instruction.

2. 发明公开

US20240194501A1 WAFER PROCESSING APPARATUS 审中-公开
公开(公告)号：US20240194501A1
公开(公告)日：2024-06-13
申请号：US18529690
申请日：2023-12-05
申请人： DISCO CORPORATION
发明人： Kentaro IIZUKA , Kazuya HIRATA , Hayato IGA , Hironobu OZAWA , Mato HATTORI , Hideo IWATA
IPC分类号： H01L21/67 , B23K26/364
CPC分类号： H01L21/67092 , B23K26/364 , H01L21/67155 , H01L21/67242
摘要： A processing apparatus includes a chuck table for holding a bonded wafer thereon, a grinding unit for grinding the bonded wafer, a cleaning unit for cleaning the bonded wafer, and a processing unit for removing a beveled portion of an outer circumferential end portion of the bonded wafer before the grinding unit grinds the bonded wafer. The processing unit includes a support for supporting the bonded wafer with a surface thereof being exposed and a laser beam applying unit for emitting a laser beam having a wavelength transmittable through the wafer. The laser beam applying unit applies the laser beam to the wafer supported on the support, from the exposed surface, while positioning a focused spot thereof within the outer circumferential excessive region of the wafer, to form a modified layer in the wafer along which to remove the beveled portion from the wafer.

3. 发明授权

US10840116B2 Wafer producing apparatus 有权
公开(公告)号：US10840116B2
公开(公告)日：2020-11-17
申请号：US16661499
申请日：2019-10-23
申请人： DISCO CORPORATION
发明人： Kentaro Iizuka , Naoki Omiya
IPC分类号： B23K26/53 , B23K26/38 , B23K26/08 , H01L21/673 , H01L21/677 , H01L21/304 , B28D5/00 , B24B7/22 , H01L21/67 , B23K26/10 , B23K26/00 , B24B27/00 , B24D3/00 , B23K101/40 , B23K103/00
CPC分类号： H01L21/67155 , B23K26/0006 , B23K26/0093 , B23K26/083 , B23K26/0838 , B23K26/0869 , B23K26/10 , B23K26/38 , B23K26/53 , B24B7/228 , B24B27/0069 , B28D5/0082 , H01L21/304 , H01L21/6732 , H01L21/6773 , H01L21/67173 , H01L21/67219 , H01L21/67346 , H01L21/67706 , H01L21/67766 , H01L21/67769 , H01L21/67778 , B23K2101/40 , B23K2103/56 , B24D3/00 , H01L21/67092 , Y10T29/5139 , Y10T29/5143 , Y10T29/5196
摘要： A wafer producing apparatus includes an ingot grinding unit that grinds the upper surface of an ingot to planarize the upper surface, a laser irradiation unit that positions the focal point of a laser beam with such a wavelength as to be transmitted through the ingot to a depth corresponding to the thickness of a wafer to be produced from the upper surface of the ingot and irradiates the ingot with the laser beam to form a separation layer, a wafer separating unit that separates the wafer from the ingot, and a tray having a support part that supports the separated wafer.

4. 发明授权

US09997357B2 Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors 有权
公开(公告)号：US09997357B2
公开(公告)日：2018-06-12
申请号：US14194549
申请日：2014-02-28
申请人： Lam Research Corporation
发明人： Reza Arghavani , Samantha Tan , Bhadri N. Varadarajan , Adrien LaVoie , Ananda Banerji , Jun Qian , Shankar Swaminathan
IPC分类号： H01L21/223 , H01L21/22 , C23C16/52 , C23C16/455 , H01L21/67 , H01L21/225 , C23C16/04 , H01L29/66 , C23C16/50
CPC分类号： H01L21/223 , C23C16/045 , C23C16/45529 , C23C16/45544 , C23C16/50 , C23C16/52 , H01L21/2225 , H01L21/2252 , H01L21/67155 , H01L21/67207 , H01L29/66803
摘要： Disclosed herein are methods of doping a fin-shaped channel region of a partially fabricated 3-D transistor on a semiconductor substrate. The methods may include forming a multi-layer dopant-containing film on the substrate, forming a capping film comprising a silicon carbide material, a silicon nitride material, a silicon carbonitride material, or a combination thereof, the capping film located such that the multi-layer dopant-containing film is located in between the substrate and the capping film, and driving dopant from the dopant-containing film into the fin-shaped channel region. Multiple dopant-containing layers of the film may be formed by an atomic layer deposition process which includes adsorbing a dopant-containing film precursor such that it forms an adsorption-limited layer on the substrate and reacting adsorbed dopant-containing film precursor. Also disclosed herein are multi-station substrate processing apparatuses for doping the fin-shaped channel regions of partially fabricated 3-D transistors.

5. 发明申请

US20170168477A1 MATCHING PROCESS CONTROLLERS FOR IMPROVED MATCHING OF PROCESS 审中-公开
公开(公告)号：US20170168477A1
公开(公告)日：2017-06-15
申请号：US15444647
申请日：2017-02-28
申请人： Applied Materials, Inc.
发明人： James Robert Moyne , Jimmy Iskandar
IPC分类号： G05B19/418 , F27B17/00 , H01L21/67 , G03F7/20
CPC分类号： G05B19/41875 , C23C16/00 , F27B17/0025 , G03F7/705 , G03F7/70608 , G03F7/70616 , G03F7/70625 , G03F7/70633 , G03F7/7065 , G03F7/70683 , G05B13/04 , G05B2219/2602 , G05B2219/31014 , G05B2219/32096 , G05B2219/32097 , G05B2219/45028 , G05B2219/45031 , G05B2219/45032 , H01L21/67155 , H01L21/67253 , H01L22/20 , H05K3/00 , Y02P80/114 , Y02P90/20 , Y02P90/86
摘要： Described herein are methods and systems for chamber matching in a manufacturing facility. A method may include receiving a first chamber recipe advice for a first chamber and a second chamber recipe advice for a second chamber. The chamber recipe advices describe a set of tunable inputs and a set of outputs for a process. The method may further include adjusting at least one of the set of first chamber input parameters or the set of second chamber input parameters and at least one of the set of first chamber output parameters or the set of second chamber output parameters to substantially match the first and second chamber recipe advices.

6. 发明申请

US20170110350A1 SERVICE TUNNEL FOR USE ON CAPITAL EQUIPMENT IN SEMICONDUCTOR MANUFACTURING AND RESEARCH FABS 审中-公开
公开(公告)号：US20170110350A1
公开(公告)日：2017-04-20
申请号：US15296547
申请日：2016-10-18
申请人： Lam Research Corporation
发明人： David Trussell , John Daugherty , Michael Kellogg , Christopher Pena , Richard Gould , Klay Kunkel
IPC分类号： H01L21/67 , H01L21/677
CPC分类号： H01L21/67173 , H01L21/67155 , H01L21/67167 , H01L21/67178 , H01L21/67184 , H01L21/67201 , H01L21/67706 , H01L21/67727 , H01L21/67733 , H01L21/67745
摘要： A system for processing substrates is provided, comprising: a wafer transport assembly that is configured to transport wafers to and from one or more process modules, the wafer transport assembly having at least one wafer transport module, wherein lateral sides of the at least one wafer transport module are configured to couple to the one or more process modules; a service floor defined below the wafer transport assembly, the service floor being defined at a height that is less than a height of a fabrication facility floor in which the system is disposed.

7. 发明授权

US09606519B2 Matching process controllers for improved matching of process 有权
公开(公告)号：US09606519B2
公开(公告)日：2017-03-28
申请号：US14223780
申请日：2014-03-24
申请人： Applied Materials, Inc.
发明人： James Robert Moyne , Jimmy Iskandar
IPC分类号： C23C16/00 , F27B17/00 , G03F7/20 , G05B13/04 , G05B19/418 , H01L21/66 , H01L21/67 , H05K3/00 , H05K13/00 , H05K13/08
CPC分类号： G05B19/41875 , C23C16/00 , F27B17/0025 , G03F7/705 , G03F7/70608 , G03F7/70616 , G03F7/70625 , G03F7/70633 , G03F7/7065 , G03F7/70683 , G05B13/04 , G05B2219/2602 , G05B2219/31014 , G05B2219/32096 , G05B2219/32097 , G05B2219/45028 , G05B2219/45031 , G05B2219/45032 , H01L21/67155 , H01L21/67253 , H01L22/20 , H05K3/00 , H05K13/00 , H05K13/08 , Y02P80/114 , Y02P80/30 , Y02P90/20 , Y02P90/86
摘要： Described herein are methods and systems for chamber matching in a manufacturing facility. A method may include receiving a first chamber recipe advice for a first chamber and a second chamber recipe advice for a second chamber. The chamber recipe advices describe a set of tunable inputs and a set of outputs for a process. The method may further include adjusting at least one of the set of first chamber input parameters or the set of second chamber input parameters and at least one of the set of first chamber output parameters or the set of second chamber output parameters to substantially match the first and second chamber recipe advices.

8. 发明申请

US20160336204A1 CHAMBER FOR DEGASSING SUBSTRATES 有权
标题翻译：用于分解底物的室
公开(公告)号：US20160336204A1
公开(公告)日：2016-11-17
申请号：US15111537
申请日：2015-12-10
申请人： EVATEC AG
发明人： Jurgen Weichart
IPC分类号： H01L21/67 , H01L21/324
CPC分类号： H01L21/67155 , H01L21/324 , H01L21/67017 , H01L21/67098 , H01L21/67161 , H01L21/67167 , H01L21/67178 , H01L21/67184 , H01L21/67207
摘要： A heater or cooler chamber for a batch of more than one workpiece includes a heat storage block. In the block a multitude of pockets are provided, whereby each of the pockets may be closed or opened by a controllably operated door. A heater or cooler arrangement is applied. The pockets are tailored to surround a workpiece applied therein in a non-contact closely spaced manner.
摘要翻译：用于一批以上工件的加热器或冷却器室包括储热块。在该块中设有许多口袋，由此可以通过可控操作的门将每个口袋封闭或打开。应用加热器或冷却器装置。这些口袋被定制成围绕以非接触紧密间隔的方式施加在其上的工件。

9. 发明授权

US09236281B2 Heating a furnace for the growth of semiconductor material 有权
标题翻译：加热炉用于生长半导体材料
公开(公告)号：US09236281B2
公开(公告)日：2016-01-12
申请号：US14234357
申请日：2012-07-19
申请人： Per Bakke , Egor Vladimirov , Pouria Homayonifar , Alexandre Teixeira
发明人： Per Bakke , Egor Vladimirov , Pouria Homayonifar , Alexandre Teixeira
IPC分类号： H01L21/00 , H01L21/67 , C30B11/00 , H01L21/324
CPC分类号： H01L21/67098 , C30B11/002 , C30B11/003 , H01L21/324 , H01L21/67155
摘要： A multi-ingot furnace for the growth of crystalline semiconductor material has one or more heating devices for heating a hot zone in which crucibles containing semiconductor material are received. At least one of the heating devices is arranged to apply a predetermined differential heat flux profile across a horizontal cross-section of the semiconductor material in one or more of the crucibles, the predetermined differential heat flux profile being selected in dependence the position of the one or more crucibles in an array. In this manner, the heating device can at least partially compensate for differences in the temperature across the semiconductor material that arises from its geometric position in the furnace. This reduces the possibility of defects such as dislocations during the growth of a crystalline semiconductor material. Associated methods are also disclosed.
摘要翻译：用于生长晶体半导体材料的多晶锭炉具有用于加热其中容纳有半导体材料的坩埚的热区域的一个或多个加热装置。至少一个加热装置被布置成在一个或多个坩埚中跨越半导体材料的水平横截面施加预定的差分热通量分布，根据该一个的位置来选择预定的差分热通量分布或更多的坩埚。以这种方式，加热装置可以至少部分地补偿由其在炉中的几何位置产生的跨越半导体材料的温度差。这降低了晶体半导体材料生长期间的诸如位错之类的缺陷的可能性。还公开了相关方法。

10. 发明授权

US09184333B2 Contact and interconnect metallization for solar cells 有权
标题翻译：太阳能电池的接触和互连金属化
公开(公告)号：US09184333B2
公开(公告)日：2015-11-10
申请号：US13791067
申请日：2013-03-08
申请人： Applied Materials, Inc.
发明人： Suketu Arun Parikh , Jen Shu , James M. Gee
IPC分类号： H01L31/0224 , H01L31/18 , H01L21/67 , H01L31/0216 , H01L31/068
CPC分类号： H01L31/1864 , H01L21/67155 , H01L31/02167 , H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521 , Y10T29/41
摘要： A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.
摘要翻译：制造线包括被配置为纹理衬底的纹理化模块，被配置为形成发射极区域的发射器模块，被配置为形成钝化层的钝化层模块，被配置为形成屏障接触区域的阻挡接触模块，被配置为将所述阻挡接触区域退火，配置成形成顶部金属接触区域的顶部金属接触模块以及被配置为将所述阻挡接触区域焊接到所述顶部金属接触区域的焊接模块。这些模块由一个或多个自动衬底处理器集成到单个制造线中。一种制造太阳能电池的方法包括在自动化生产线中依次进行：在衬底中掺杂掺杂剂; 设置钝化层; 处理和退火阻挡金属浆料以形成屏障接触; 并且配置和退火金属接触膏以形成顶部金属接触区域。

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