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1. 发明授权

US09922894B1 Air cavity packages and methods for the production thereof 有权
公开(公告)号：US09922894B1
公开(公告)日：2018-03-20
申请号：US15269629
申请日：2016-09-19
申请人： FREESCALE SEMICONDUCTOR INC.
发明人： Lakshminarayan Viswanathan , Jaynal A. Molla , David Abdo , Mali Mahalingam , Carl D'Acosta
IPC分类号： H01L23/12 , H01L23/66 , H01L23/20 , H01L23/047 , H01L21/48 , H01L23/057 , H01L23/367 , B22F3/10 , B22F1/00 , B23K35/02 , B23K35/30 , H01L23/00
CPC分类号： H01L23/20 , B22F1/0062 , B22F3/10 , B22F5/10 , B22F7/02 , B22F2301/10 , B22F2301/255 , B22F2302/45 , B23K35/025 , B23K35/30 , H01L21/4817 , H01L21/50 , H01L23/04 , H01L23/047 , H01L23/057 , H01L23/10 , H01L23/3675 , H01L24/32 , H01L24/49 , H01L24/73 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48106 , H01L2224/48177 , H01L2224/73265 , H01L2924/01042 , H01L2924/15747 , H01L2924/3511
摘要： Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.

2. 发明申请

US20180053702A1 3D Printed Hermetic Package Assembly and Method 审中-公开
公开(公告)号：US20180053702A1
公开(公告)日：2018-02-22
申请号：US15792225
申请日：2017-10-24
申请人： Erick Merle Spory
发明人： Erick Merle Spory
IPC分类号： H01L23/20 , H01L23/00 , H01L21/48 , H01L23/04 , H01L23/495 , H01L23/498 , H01L21/50 , H01L23/26
CPC分类号： H01L23/20 , H01L21/4803 , H01L21/4817 , H01L21/50 , H01L23/04 , H01L23/10 , H01L23/26 , H01L23/49513 , H01L23/49541 , H01L23/49861 , H01L23/564 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L2224/24011 , H01L2224/24051 , H01L2224/24175 , H01L2224/245 , H01L2224/25171 , H01L2224/2731 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/48 , H01L2224/73267 , H01L2224/82102 , H01L2224/82103 , H01L2224/82214 , H01L2224/82815 , H01L2224/83192 , H01L2224/838 , H01L2224/8385 , H01L2224/92247 , H01L2924/00 , H01L2924/00014 , H01L2924/00015 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19107 , H01L2924/3656 , H01L2924/3861
摘要： A method is provided. The method includes one or more of removing existing ball bonds from an extracted die, placing the extracted die into a recess of a hermetic substrate, the extracted die having a centered orientation in the recess, and applying a side fill compound into the recess between the extracted die and the hermetic substrate. The method also includes 3D printing, by a 3D printer, a plurality of bond connections between die pads of the extracted die and first bond pads of the hermetic substrate in order to create a 3D printed die substrate, and 3D printing a hermetic encapsulation over the die, the side fill compound, and the 3D printed bond connections in order to create a hermetic assembly. The extracted die includes a fully functional semiconductor die removed from a previous package. The hermetic substrate includes the first bond pads coupled to second bond pads.

3. 发明申请

US20180040529A1 Remapped Packaged Extracted Die with 3D Printed Bond Connections 审中-公开
公开(公告)号：US20180040529A1
公开(公告)日：2018-02-08
申请号：US15792381
申请日：2017-10-24
申请人： Erick Merle Spory
发明人： Erick Merle Spory
IPC分类号： H01L23/20 , H01L21/48 , H01L23/04 , H01L23/498 , H01L21/50 , H01L23/26 , H01L23/00 , H01L23/495
CPC分类号： H01L23/20 , H01L21/4803 , H01L21/4817 , H01L21/4867 , H01L21/50 , H01L23/04 , H01L23/057 , H01L23/10 , H01L23/26 , H01L23/49513 , H01L23/49541 , H01L23/49838 , H01L23/49861 , H01L23/564 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L2224/24011 , H01L2224/24051 , H01L2224/24175 , H01L2224/245 , H01L2224/25171 , H01L2224/2731 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/48 , H01L2224/82102 , H01L2224/82103 , H01L2224/82214 , H01L2224/82815 , H01L2224/83192 , H01L2224/838 , H01L2224/8385 , H01L2224/92247 , H01L2924/00 , H01L2924/00014 , H01L2924/00015 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/3656 , H01L2924/3861
摘要： An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

4. 发明申请

US20170186731A1 SOLID STATE DRIVE OPTIMIZED FOR WAFERS 审中-公开
公开(公告)号：US20170186731A1
公开(公告)日：2017-06-29
申请号：US15166038
申请日：2016-05-26
申请人： SANDISK TECHNOLOGIES LLC
发明人： Atsuyoshi Koike
IPC分类号： H01L25/065 , H01L23/48 , H01L23/02 , H01L25/18 , H01L23/367 , H01L23/00 , H01L23/20 , H01L23/467 , H01L23/473 , G11C29/04 , G11C16/04 , H01L25/00
CPC分类号： H01L25/0657 , G11C5/04 , G11C16/0483 , G11C29/04 , G11C29/765 , G11C2029/0403 , H01L23/02 , H01L23/20 , H01L23/3675 , H01L23/467 , H01L23/473 , H01L23/481 , H01L24/14 , H01L25/18 , H01L25/50 , H01L27/11556 , H01L27/11582 , H01L2225/06541 , H01L2225/06582 , H01L2225/06589
摘要： An SSD with a package optimized for semiconductor wafers is configured by thinning a plurality of undiced wafers and stacking the wafers. The wafers are connected to each other by TSV. A subset of the wafers include memory circuits. One of the wafer not in the subset includes peripheral circuits. A casing houses the wafers.

5. 发明申请

US20160126623A1 ANTENNA IMPEDANCE MATCHING AND APERTURE TUNING CIRCUITRY 审中-公开
标题翻译：天线阻抗匹配和孔径调谐电路
公开(公告)号：US20160126623A1
公开(公告)日：2016-05-05
申请号：US14931720
申请日：2015-11-03
申请人： RF Micro Devices, Inc.
发明人： George Maxim , Dirk Robert Walter Leipold , Marcus Granger-Jones , Baker Scott
IPC分类号： H01Q1/50
CPC分类号： H01L23/315 , H01L21/02266 , H01L21/02282 , H01L21/304 , H01L21/30604 , H01L21/565 , H01L21/6835 , H01L23/20 , H01L23/291 , H01L23/293 , H01L23/3121 , H01L23/3135 , H01L23/36 , H01L23/367 , H01L23/3731 , H01L23/3737 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/562 , H01L24/17 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/92125 , H01L2924/0002 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01Q1/50 , H05K1/0203 , H05K1/181 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要： Antenna aperture tuning circuitry includes a first signal path and a second signal path coupled in parallel between an antenna radiating element and ground. A first LC resonator and a second LC resonator are each coupled between the first signal path and ground. The first LC resonator and the second LC resonator are electromagnetically coupled such that a coupling factor between the first LC resonator and the second LC resonator is between about 1.0% and 40.0%. A third LC resonator and a fourth LC resonator are each coupled between the second signal path and ground. The third LC resonator and the fourth LC resonator are electromagnetically coupled such that a coupling factor between the third LC resonator and the fourth LC resonator is between about 1.0% and 40.0%.
摘要翻译：天线孔径调谐电路包括在天线辐射元件和地之间并联耦合的第一信号路径和第二信号路径。第一LC谐振器和第二LC谐振器各自耦合在第一信号路径和地之间。第一LC谐振器和第二LC谐振器被电磁耦合，使得第一LC谐振器和第二LC谐振器之间的耦合因子在约1.0％和40.0％之间。第三LC谐振器和第四LC谐振器各自耦合在第二信号路径和地之间。第三LC谐振器和第四LC谐振器被电磁耦合，使得第三LC谐振器和第四LC谐振器之间的耦合因子在约1.0％和40.0％之间。

6. 发明授权

US08237171B2 High voltage high package pressure semiconductor package 有权
标题翻译：高压高封装压力半导体封装
公开(公告)号：US08237171B2
公开(公告)日：2012-08-07
申请号：US12658576
申请日：2010-02-09
申请人： Tracy Autry
发明人： Tracy Autry
IPC分类号： H01L29/15
CPC分类号： H01L23/20 , H01L23/051 , H01L23/10 , H01L2924/0002 , H01L2924/00
摘要： A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.
摘要翻译：一种密封的集成电路封装，其包括容纳半导体管芯的腔体，由此在组装期间和形成时腔体被加压。本发明防止了当封装在大气压下经受高温然后在高电压下降低管芯的性能而被冷却时产生的封装上的应力。通过在具有惰性气体的气氛中在高压（例如高达50PSIG）下封装模具，并且在完成的封装中提供大的压力，模具在较高的电压下显着地不太可能发生电弧，从而允许实现单片封装最多可操作至少1200伏。此外，本发明被配置为使用与可在较高温度下处理的碳化硅模具相容的钎焊元件。

7. 发明申请

US20100270667A1 SEMICONDUCTOR PACKAGE WITH MULTIPLE CHIPS AND SUBSTRATE IN METAL CAP 有权
标题翻译：具有多个晶片和基板的金属封装的半导体封装
公开(公告)号：US20100270667A1
公开(公告)日：2010-10-28
申请号：US12429541
申请日：2009-04-24
申请人： Chong Yee Tong , Hui Teng Wang
发明人： Chong Yee Tong , Hui Teng Wang
IPC分类号： H01L23/20 , H01L23/498 , H01L21/98
CPC分类号： H01L23/055 , H01L23/20 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L25/0652 , H01L25/0657 , H01L2224/16 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48465 , H01L2224/73253 , H01L2225/0651 , H01L2225/06517 , H01L2225/06572 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01068 , H01L2924/01079 , H01L2924/15311 , H01L2924/16152 , H01L2924/16172 , H01L2924/16747 , H01L2924/19107 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a first substrate, a second substrate and a metal cap. The chips are electrically connected to the first substrate, the second substrate is disposed between the chips, and the chips and the second substrate are disposed within the metal cap.
摘要翻译：半导体封装包括第一半导体芯片，第二半导体芯片，第一基板，第二基板和金属盖。芯片电连接到第一基板，第二基板设置在芯片之间，并且芯片和第二基板设置在金属盖内。

8. 发明授权

US07335965B2 Packaging of electronic chips with air-bridge structures 有权
标题翻译：用气桥结构包装电子芯片
公开(公告)号：US07335965B2
公开(公告)日：2008-02-26
申请号：US10931510
申请日：2004-09-01
申请人： Paul A. Farrar
发明人： Paul A. Farrar
IPC分类号： H01L29/00 , H01L23/48
CPC分类号： H01L23/5329 , H01L21/7682 , H01L23/20 , H01L23/3677 , H01L23/4821 , H01L23/5222 , H01L23/66 , H01L2924/0002 , H01L2924/1433 , Y10S438/977 , H01L2924/00
摘要： A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.
摘要翻译：一种用于制造空气桥结构的电路组件和制造能够支撑包括空气桥结构的电路组件的集成电路封装的方法。电路组件包括电子芯片和嵌入多个具有多个蒸发温度的材料中的导电结构。多个材料形成在电子芯片上，并且导电结构耦合到电子芯片。为了制造电路组件，在电子芯片上形成包括间隙的支撑结构。支撑结构的间隙填充有气化温度小于支撑结构的汽化温度的材料。导电结构嵌入在支撑结构和材料中，并且连接结构安装在支撑结构上。最后，通过加热电路组件从空隙中移除材料。

9. 发明申请

US20070138622A1 Electronic device and semiconductor device 有权
标题翻译：电子设备和半导体器件
公开(公告)号：US20070138622A1
公开(公告)日：2007-06-21
申请号：US11637878
申请日：2006-12-13
申请人： Mitsuji Nunokawa
发明人： Mitsuji Nunokawa
IPC分类号： H01L23/12
CPC分类号： H01L23/552 , H01L23/04 , H01L23/10 , H01L23/20 , H01L23/66 , H01L2224/0401 , H01L2224/04026 , H01L2224/1146 , H01L2224/13144 , H01L2224/16225 , H01L2224/274 , H01L2224/94 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/1423 , H01L2924/16152 , H01L2924/3011 , H01L2924/3025 , H01L2224/11 , H01L2224/03
摘要： An electronic device has a substrate, a conductive layer and a substrate mounted portion. The substrate has a circuit portion used from 60 GHz to 80 GHz. The conductive layer is provided directly on a face of the substrate that is opposite side of the circuit portion. The face having the circuit portion of the substrate is mounted face down on the substrate mounted portion. A thickness of the conductive layer is a thickness where a sheet resistance of the conductive layer is ¼ to 4 times of a resistance component of an impedance of the substrate.
摘要翻译：电子器件具有衬底，导电层和衬底安装部分。衬底具有从60GHz到80GHz使用的电路部分。导电层直接设置在基板的与电路部分相对的一侧的表面上。具有基板的电路部分的面朝下安装在基板安装部分上。导电层的厚度是导电层的薄层电阻为衬底阻抗的电阻分量的1/4至4倍的厚度。

10. 发明授权

US07017411B2 Apparatus with selected fill gas 有权
标题翻译：具有选定填充气体的装置
公开(公告)号：US07017411B2
公开(公告)日：2006-03-28
申请号：US10793382
申请日：2004-03-04
申请人： John A. Geen , John Martin
发明人： John A. Geen , John Martin
IPC分类号： G01P15/02
CPC分类号： H01L23/20 , B81B7/0058 , B81B2201/025 , H01L2924/0002 , H01L2924/00
摘要： An inertial sensor has an interior filled with a relatively low viscosity fill gas. To that end, the inertial sensor has a housing forming the noted interior, and a movable component within the interior. The inertial sensor also has the noted fill gas within the interior. The fill gas has a viscosity that is less than the viscosity of nitrogen under like conditions. For example, when subjected to the same temperatures and pressures, the fill gas has a viscosity that is less than the viscosity of nitrogen.
摘要翻译：惯性传感器具有填充有相对低粘度的填充气体的内部。为此，惯性传感器具有形成所述内部的壳体和内部的可移动部件。惯性传感器在内部还具有注明的填充气体。填充气体的粘度比同样条件下的氮的粘度小。例如，当经受相同的温度和压力时，填充气体的粘度小于氮的粘度。

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