专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190123145A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190123145A1
公开(公告)日：2019-04-25
申请号：US16216815
申请日：2018-12-11
申请人： Mitsubishi Electric Corporation
发明人： Katsumi NAKAMURA
IPC分类号： H01L29/10 , H01L21/265 , H01L29/66 , H01L27/06 , H01L29/861 , H01L29/36 , H01L21/322 , H01L21/225 , H01L29/868 , H01L21/266 , H01L21/324 , H01L29/739 , H01L29/06
CPC分类号： H01L29/1095 , H01L21/2253 , H01L21/26506 , H01L21/26513 , H01L21/266 , H01L21/3221 , H01L21/324 , H01L27/0664 , H01L29/0615 , H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/402 , H01L29/407 , H01L29/66121 , H01L29/66348 , H01L29/739 , H01L29/7397 , H01L29/8611 , H01L29/868
摘要： The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N− drift layer. A concentration slope δ, which is derived from displacements in a depth TB (μm) and an impurity concentration CB (cm−3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03≤δ≤0.7}.

2. 发明申请

US20180323338A1 ULTRAVIOLET LIGHT EMITTING DIODE WITH TUNNEL JUNCTION 审中-公开
公开(公告)号：US20180323338A1
公开(公告)日：2018-11-08
申请号：US15587269
申请日：2017-05-04
申请人： X Development LLC
发明人： Michael Grundmann , Martin F. Schubert
IPC分类号： H01L33/06 , H01L33/32 , H01L27/15 , H01L25/16 , H01L33/00 , H05B33/08
CPC分类号： H01L33/06 , H01L25/167 , H01L27/156 , H01L29/66121 , H01L29/66151 , H01L29/66219 , H01L29/8618 , H01L29/88 , H01L29/882 , H01L33/0008 , H01L33/0025 , H01L33/0045 , H01L33/0075 , H01L33/04 , H01L33/32 , H01L33/40 , H05B33/0803 , H05B33/0845
摘要： A light emitting diode (LED) to emit ultraviolet (UV) light includes a first n-type semiconductor region and a first p-type semiconductor region. The LED also includes an active region disposed between the first n-type semiconductor region and the first p-type semiconductor region, and in response to a bias applied across the light emitting diode, the active region emits UV light. A tunnel junction is disposed in the LED so the first p-type semiconductor region is disposed between the active region and the tunnel junction. The tunnel junction is electrically coupled to inject charge carriers into the active region through the first p-type semiconductor region. A second n-type semiconductor region is also disposed in the LED so the tunnel junction is disposed between the second n-type semiconductor region and the first p-type semiconductor region.

3. 发明申请

US20180040743A1 SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS 审中-公开
公开(公告)号：US20180040743A1
公开(公告)日：2018-02-08
申请号：US15670266
申请日：2017-08-07
申请人： ATOMERA INCORPORATED
发明人： ROBERT J. MEARS , Hideki Takeuchi , Marek Hytha
IPC分类号： H01L29/88 , H01L29/861 , H01L29/66 , H01L29/15
CPC分类号： H01L29/7376 , H01L27/092 , H01L29/1054 , H01L29/152 , H01L29/155 , H01L29/157 , H01L29/161 , H01L29/36 , H01L29/66007 , H01L29/6603 , H01L29/66121 , H01L29/66151 , H01L29/66477 , H01L29/66545 , H01L29/66651 , H01L29/78 , H01L29/7842 , H01L29/8618 , H01L29/882
摘要： A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.

4. 发明授权

US09882019B2 Compound varactor 有权
公开(公告)号：US09882019B2
公开(公告)日：2018-01-30
申请号：US15245468
申请日：2016-08-24
申请人： Qorvo US, Inc.
发明人： Peter V. Wright
IPC分类号： H01L29/93 , H01L29/66 , H01L29/861 , H01L27/08
CPC分类号： H01L29/66174 , H01L27/0808 , H01L29/6609 , H01L29/66121 , H01L29/66128 , H01L29/861 , H01L29/93
摘要： The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base layer arranged in a first plurality of parallel fingers directly onto the collector layer, and depositing a second base layer arranged in a second plurality of parallel fingers that are interleaved with the first plurality of parallel fingers directly onto the collector layer.

5. 发明授权

US09865748B2 Semiconductor structure and method for manufacturing the same 有权
公开(公告)号：US09865748B2
公开(公告)日：2018-01-09
申请号：US15488325
申请日：2017-04-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Hsin-Chih Chiang , Tung-Yang Lin , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/68 , H01L29/87 , H01L29/66 , H01L29/06
CPC分类号： H01L29/87 , H01L29/0607 , H01L29/66121
摘要： A semiconductor structure includes a semiconductor substrate having a first electrical portion, a second electrical portion, and a bridged conductive layer. The first electrical portion includes a first semiconductor well, a second semiconductor well in the first semiconductor well, and a third semiconductor well and a fourth semiconductor well in the second semiconductor well. The second electrical portion includes a fifth semiconductor well, a semiconductor layer in the fifth semiconductor well, and a sixth semiconductor well and a seventh semiconductor well in the fifth semiconductor well. The semiconductor layer has separated first and second portions. The bridged conductive layer connects the fourth semiconductor well and the sixth semiconductor well.

6. 发明授权

US09711634B2 Semiconductor device including a super junction MOSFET 有权
公开(公告)号：US09711634B2
公开(公告)日：2017-07-18
申请号：US14882423
申请日：2015-10-13
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takahiro Tamura , Yasuhiko Onishi
IPC分类号： H01L29/78 , H01L21/263 , H01L29/868 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/739
CPC分类号： H01L29/66666 , H01L21/263 , H01L21/265 , H01L29/06 , H01L29/0634 , H01L29/0638 , H01L29/0688 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/32 , H01L29/66121 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7803 , H01L29/7811 , H01L29/868
摘要： A super junction MOSFET includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n− region with a lower impurity concentration than the n-type drift region. With this structure, it is possible to provide a super junction MOSFET which prevents a sharp rise in hard recovery waveform during a reverse recovery operation.

7. 发明授权

US09705079B2 Tunable voltage margin access diodes 有权
公开(公告)号：US09705079B2
公开(公告)日：2017-07-11
申请号：US15343602
申请日：2016-11-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Mohit Bajaj , Arpan K. Deb , Aniruddha Konar , Kota V. R. M. Murali , Rajan K. Pandey , Kumar R. Virwani
IPC分类号： H01L29/24 , H01L29/16 , H01L45/00 , H01L27/24 , H01L27/22 , H01L29/861 , H01L21/02 , H01L29/66 , H01L29/15
CPC分类号： H01L45/1666 , B82Y10/00 , H01L21/02568 , H01L21/0262 , H01L27/224 , H01L27/2409 , H01L29/157 , H01L29/24 , H01L29/66121 , H01L29/8618 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/16 , H01L45/1608 , H01L45/165 , Y10S977/76 , Y10S977/943
摘要： The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

8. 发明申请

US20160293591A1 TRANSIENT OVERVOLTAGE PROTECTION DEVICE 有权
标题翻译：瞬态过电压保护装置
公开(公告)号：US20160293591A1
公开(公告)日：2016-10-06
申请号：US14678005
申请日：2015-04-03
申请人： LITTELFUSE, INC.
发明人： Gary Mark Bentley , James Allan Peters , Steve Wilton Byatt
IPC分类号： H01L27/02 , H01L29/66
CPC分类号： H01L27/0255 , H01L29/0661 , H01L29/66121 , H01L29/861
摘要： In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100 V when an external voltage is applied between the first surface region and second surface region.
摘要翻译：在一个实施例中，过电压保护装置可以包括包括n型体区域的半导体衬底。过电压保护装置还可以包括设置在半导体衬底的第一表面区域中的第一p型区域，以及与n型体区域形成第一P / N结，以及第二p型区域，所述半导体衬底与所述第一表面相对的第二表面区域，以及与所述n型体区域形成第二P / N结，其中所述n型体区域，第一p型区域和第二p型区域形成当在第一表面区域和第二表面区域之间施加外部电压时，具有大于100V的击穿电压的击穿装置。

9. 发明申请

US20160284995A1 TUNABLE VOLTAGE MARGIN ACCESS DIODES 有权
公开(公告)号：US20160284995A1
公开(公告)日：2016-09-29
申请号：US15132675
申请日：2016-04-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Mohit Bajaj , Arpan K. Deb , Aniruddha Konar , Kota V. R. M. Murali , Rajan K. Pandey , Kumar R. Virwani
IPC分类号： H01L45/00
CPC分类号： H01L45/1666 , B82Y10/00 , H01L21/02568 , H01L21/0262 , H01L27/224 , H01L27/2409 , H01L29/157 , H01L29/24 , H01L29/66121 , H01L29/8618 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/16 , H01L45/1608 , H01L45/165 , Y10S977/76 , Y10S977/943
摘要： The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

10. 发明申请

US20160284870A1 TUNABLE VOLTAGE MARGIN ACCESS DIODES 有权
标题翻译：电压电压接入二极管
公开(公告)号：US20160284870A1
公开(公告)日：2016-09-29
申请号：US14665261
申请日：2015-03-23
申请人： International Business Machines Corporation
发明人： Mohit Bajaj , Arpan K. Deb , Aniruddha Konar , Kota V. R. M. Murali , Rajan K. Pandey , Kumar R. Virwani
IPC分类号： H01L29/861 , H01L29/24 , H01L29/15 , H01L29/66
CPC分类号： H01L45/1666 , B82Y10/00 , H01L21/02568 , H01L21/0262 , H01L27/224 , H01L27/2409 , H01L29/157 , H01L29/24 , H01L29/66121 , H01L29/8618 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/142 , H01L45/16 , H01L45/1608 , H01L45/165 , Y10S977/76 , Y10S977/943
摘要： The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.
摘要翻译：本发明一般涉及高电流密度访问装置（AD），更具体地说，涉及使用含铜混合离子电子传导层的相变存储器（PCM）块中形成可调电压余量存取二极管的结构和方法（MIEC）材料。本发明的实施例可以使用层MIEC材料来形成可以提供高电流密度并且在与标准BEOL处理兼容的温度下制造时可靠地操作的接入装置。通过改变沉积技术和使用的MIEC材料的量，可将接入设备的电压余量（即，器件导通的电压和电流高于本底噪声）调谐到不同存储器件的特定操作条件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式