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1. 发明申请

US20070096239A1 Semiconductor devices and methods of manufacture 审中-公开
标题翻译：半导体器件及制造方法
公开(公告)号：US20070096239A1
公开(公告)日：2007-05-03
申请号：US11263163
申请日：2005-10-31
申请人： Xian-An Cao , Stephen Arthur
发明人： Xian-An Cao , Stephen Arthur
IPC分类号： H01L31/00
CPC分类号： H01L29/868 , H01L29/1608 , H01L29/2003 , H01L29/66196 , H01L29/66204 , H01L29/872
摘要： A semiconductor device includes a substrate comprising a material selected from the group consisting of AlN, SiC, GaN, sapphire and combinations thereof. An n+ type epitaxial layer is disposed above substrate and comprises GaN or AlGaN. An n− type epitaxial layer is disposed above substrate and comprises GaN or AlGaN. A p+-n junction grid comprising p+ GaN or p+ AlGaN is formed on selective areas of the n− type epitaxial layer. A metal layer is disposed over the p+-n junction grid and forms a Schottky contact. Another metal layer is deposited on one of the substrate and the n+ type epitaxial layer and forms a cathode electrode. A method of fabricating a semiconductor device is provided and includes forming a p+-n junction grid on a drift layer comprising GaN or AlGaN.
摘要翻译：半导体器件包括包含选自由AlN，SiC，GaN，蓝宝石及其组合组成的组的材料的衬底。 n + +型外延层设置在衬底上方并包括GaN或AlGaN。 n型外延层设置在衬底上方并且包括GaN或AlGaN。在n型外延层的选择性区域上形成包括p + +或/或+ AlGaN的p + 金属层设置在p + n + n连接栅格上方并形成肖特基接触。另一金属层沉积在衬底和n +型外延层中的一个上并形成阴极电极。提供了一种制造半导体器件的方法，包括在包括GaN或AlGaN的漂移层上形成p + + n结栅格。

2. 发明申请

US20130292790A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130292790A1
公开(公告)日：2013-11-07
申请号：US13930352
申请日：2013-06-28
申请人： FUJITSU LIMITED
发明人： Yuichi Minoura , NAOYA OKAMOTO
IPC分类号： H01L29/872 , H01L29/66
CPC分类号： H01L29/872 , H01L21/2654 , H01L24/73 , H01L27/0814 , H01L27/095 , H01L29/2003 , H01L29/417 , H01L29/42316 , H01L29/475 , H01L29/66143 , H01L29/66196 , H01L29/66462 , H01L29/7787 , H01L2224/32245 , H01L2224/45124 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2924/12032 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.
摘要翻译：半导体器件包括半导体层和肖特基电极，在半导体层和肖特基电极之间形成肖特基结。肖特基电极包括含有金属的金属部分，在半导体层和金属部分之间形成肖特基结; 以及围绕所述金属部分的氮化物部分，所述氮化物部分包含所述金属的氮化物，以及在所述半导体层和所述氮化物部分之间形成肖特基结。

3. 发明申请

US20040104384A1 Growth of high temperature, high power, high speed electronics 审中-公开
标题翻译：增长高温，高功率，高速电子
公开(公告)号：US20040104384A1
公开(公告)日：2004-06-03
申请号：US10419294
申请日：2003-04-21
发明人： Theodore D. Moustakas , William Stacey , Philip Lamarre , Robert Scott Morris
IPC分类号： H01L029/06 , H01L031/0328 , H01L031/0336 , H01L031/072 , H01L031/109 , H01L031/0312 , H01L021/331 , H01L021/8222
CPC分类号： C30B29/40 , C30B23/02 , C30B25/18 , H01L21/02378 , H01L21/0254 , H01L21/02658 , H01L21/02661 , H01L29/2003 , H01L29/66196 , H01L29/66318
摘要： High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as SiC or sapphire by forming a compliant substrate for the growing the monocrystalline layers. Devices and methods for fabricating silicon carbide based heterojunction bipolar devices such as transistors and diodes. These devices are suitable for high power and/or high speed and/or high temperature electronic applications.
摘要翻译：通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长成覆盖在单晶衬底例如SiC或蓝宝石上。用于制造基于碳化硅的异质结双极器件如晶体管和二极管的器件和方法。这些器件适用于大功率和/或高速和/或高温电子应用。

4. 发明授权

US09035414B2 Compound semiconductor device and manufacturing method thereof 有权
标题翻译：化合物半导体器件及其制造方法
公开(公告)号：US09035414B2
公开(公告)日：2015-05-19
申请号：US13930352
申请日：2013-06-28
申请人： FUJITSU LIMITED
发明人： Yuichi Minoura , Naoya Okamoto
IPC分类号： H01L29/47 , H01L21/28 , H01L21/44 , H01L29/872 , H01L27/08 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/778 , H01L27/095 , H01L29/20 , H01L21/265
CPC分类号： H01L29/872 , H01L21/2654 , H01L24/73 , H01L27/0814 , H01L27/095 , H01L29/2003 , H01L29/417 , H01L29/42316 , H01L29/475 , H01L29/66143 , H01L29/66196 , H01L29/66462 , H01L29/7787 , H01L2224/32245 , H01L2224/45124 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L2924/12032 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.
摘要翻译：半导体器件包括半导体层和肖特基电极，在半导体层和肖特基电极之间形成肖特基结。肖特基电极包括含有金属的金属部分，在半导体层和金属部分之间形成肖特基结; 以及围绕所述金属部分的氮化物部分，所述氮化物部分包含所述金属的氮化物，以及在所述半导体层和所述氮化物部分之间形成肖特基结。

5. 发明授权

US5485017A Semiconductor device and method of manufacturing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5485017A
公开(公告)日：1996-01-16
申请号：US241447
申请日：1994-05-11
申请人： Jun-ichi Nishizawa
发明人： Jun-ichi Nishizawa
IPC分类号： H01L21/329 , H01L29/739 , H01L29/861 , H01L29/06 , H01L21/265
CPC分类号： H01L29/66356 , H01L29/66196 , H01L29/739 , H01L29/8616
摘要： A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus. The metal electrodes and the source electrode are formed by depositing a metal and a low-resistance semiconductor selectively or both in one location within the growing apparatus.
摘要翻译：半导体器件在各个n +漏极区域上具有n +源极区，第一n沟道区，势垒层，第二n沟道区，一对n +漏极区，绝缘膜和一对金属电极，全部依次设置在n +晶体基板的上表面上。漏极区域和金属电极共同提供存储电容。源电极设置在n +晶体基板的下表面上。通过穿过阻挡层可以高速写入和读取位信息。根据制造上述半导体器件的方法，依次沉积n +源极区，第一n-沟道区，势垒层，第二n-沟道区，n +漏极区，绝缘膜和金属电极在生长装置中的n +晶体衬底上。金属电极和源电极通过在生长装置内的一个位置中选择性地或两者沉积金属和低电阻半导体而形成。

6. 发明申请

US20120068304A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120068304A1
公开(公告)日：2012-03-22
申请号：US12885704
申请日：2010-09-20
申请人： Thoralf KAUTZSCH
发明人： Thoralf KAUTZSCH
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L21/743 , H01L29/66181 , H01L29/66196
摘要： One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming an opening within the substrate; forming a conductive layer within the opening; and forming a semiconductor layer over the conductive layer.
摘要翻译：一个或多个实施例涉及一种形成半导体结构的方法，包括：提供半导体衬底; 在衬底内形成开口; 在开口内形成导电层; 以及在所述导电层上形成半导体层。

7. 发明授权

US06245628B1 Method of manufacturing a resistor in a semiconductor device 失效
标题翻译：在半导体器件中制造电阻器的方法
公开(公告)号：US06245628B1
公开(公告)日：2001-06-12
申请号：US09031039
申请日：1998-02-26
申请人： Takeshi Fukui , Hidetoshi Furukawa , Daisuke Ueda
发明人： Takeshi Fukui , Hidetoshi Furukawa , Daisuke Ueda
IPC分类号： H01L21265
CPC分类号： H01L29/66196 , H01L29/8605
摘要： A resistive area 7 is formed selectively on a semi-insulating substrate 1, and ohmic electrodes 10 are formed on both ends of the resistive area. Then a photo resist 14 having an opening 13 between the electrodes 10 is so formed as not completely across the resistive area 7. A desirable resistance value is thus obtained by removing the resistance area 7 by etching through the opening 13 gradually.
摘要翻译：选择性地在半绝缘基板1上形成电阻区域7，并且在电阻区域的两端形成欧姆电极10。然后，在电极10之间具有开口13的光致抗蚀剂14形成为不完全穿过电阻区域7.因此通过逐渐通过开口13进行蚀刻去除电阻区域7，从而获得所需的电阻值。

8. 发明授权

US5557141A Method of doping, semiconductor device, and method of fabricating semiconductor device 失效
标题翻译：掺杂方法，半导体器件和制造半导体器件的方法
公开(公告)号：US5557141A
公开(公告)日：1996-09-17
申请号：US220542
申请日：1994-03-30
申请人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
发明人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
IPC分类号： H01L21/18 , H01L21/22 , H01L21/225 , H01L21/285 , H01L21/314 , H01L21/324 , H01L21/329 , H01L21/335 , H01L21/338 , H01L21/8252 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/775 , H01L29/778 , H01L29/812 , H01L29/8605 , H01L23/58 , H01L29/00 , H01L29/06 , H01L31/0328
CPC分类号： B82Y10/00 , H01L21/22 , H01L21/2258 , H01L21/28587 , H01L21/28593 , H01L21/3144 , H01L21/3245 , H01L21/8252 , H01L27/0605 , H01L29/0891 , H01L29/1025 , H01L29/66075 , H01L29/66196 , H01L29/66462 , H01L29/66469 , H01L29/66856 , H01L29/66871 , H01L29/66878 , H01L29/66977 , H01L29/775 , H01L29/7787 , H01L29/812 , H01L29/8122 , H01L29/8605 , Y10S148/034 , Y10S438/962
摘要： A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.
摘要翻译：在III-V族化合物半导体的晶体上形成掺杂有杂质的III-V族化合物半导体的晶体，具有SiO x的未掺杂膜和防止V族原子扩散的膜（例如SiN膜） SiO x膜中的硅扩散到III-V族化合物半导体中，从而形成掺杂层。

9. 发明授权

US5350709A Method of doping a group III-V compound semiconductor 失效
标题翻译：掺杂III-V族化合物半导体的方法
公开(公告)号：US5350709A
公开(公告)日：1994-09-27
申请号：US75232
申请日：1993-06-10
申请人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
发明人： Yasoo Harada , Shigeharu Matsushita , Satoshi Terada , Emi Fujii , Takashi Kurose , Takayoshi Higashino , Takashi Yamada , Akihito Nagamatsu , Daijirou Inoue , Kouji Matsumura
IPC分类号： H01L21/18 , H01L21/22 , H01L21/225 , H01L21/285 , H01L21/314 , H01L21/324 , H01L21/329 , H01L21/335 , H01L21/338 , H01L21/8252 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/775 , H01L29/778 , H01L29/812 , H01L29/8605
CPC分类号： B82Y10/00 , H01L21/22 , H01L21/2258 , H01L21/28587 , H01L21/28593 , H01L21/3144 , H01L21/3245 , H01L21/8252 , H01L27/0605 , H01L29/0891 , H01L29/1025 , H01L29/66075 , H01L29/66196 , H01L29/66462 , H01L29/66469 , H01L29/66856 , H01L29/66871 , H01L29/66878 , H01L29/66977 , H01L29/775 , H01L29/7787 , H01L29/812 , H01L29/8122 , H01L29/8605 , Y10S148/034 , Y10S438/962
摘要： A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.
摘要翻译：掺杂III-V族化合物半导体与杂质的方法，其中在未掺杂的SiOx膜和用于防止V族原子扩散的膜（例如，SiN膜）之后，依次形成在组的晶体上 III-V族化合物半导体，对该样品进行至少一次热处理以使SiOx膜中的硅扩散到III-V族化合物半导体中，从而形成掺杂层。使用这种掺杂层形成方法，制造场效应晶体管，二极管，电阻层，二维电子气或一维量子线，零维量子箱，电子波干涉装置等。

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