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    • 2. 发明申请
    • AMPLIFIER WITH BIAS STABILIZER
    • 放大器与偏置稳压器
    • US20100264987A1
    • 2010-10-21
    • US12763505
    • 2010-04-20
    • Tachio YUASA
    • Tachio YUASA
    • H03F3/45H03F3/04
    • H03F3/45183H03F1/086H03F2203/45456H03F2203/45511H03F2203/45628H03F2203/45648
    • An amplifier with bias stabilizer includes first to forth transistors, an amplifier unit and a resistor. The first transistor and the second transistor are connected in series between first and second power supplies and generate a first current. The third transistor is connected in a current mirror configuration to the second transistor and generates a second current corresponding to the first current. The amplifier unit generates an output signal based on an input signal and includes a fourth transistor, the fourth transistor generating a control voltage according to the second current so as to control the first transistor. The resistor is connected in series to at least one of the first to fourth transistors.
    • 具有偏置稳压器的放大器包括第一至第四晶体管,放大器单元和电阻器。 第一晶体管和第二晶体管串联连接在第一和第二电源之间并产生第一电流。 第三晶体管以电流镜配置连接到第二晶体管,并产生对应于第一电流的第二电流。 放大器单元基于输入信号生成输出信号,并且包括第四晶体管,第四晶体管根据第二电流产生控制电压,以便控制第一晶体管。 电阻器与第一至第四晶体管中的至少一个串联连接。
    • 6. 发明申请
    • Bipolar differential amplifier
    • 双极差分放大器
    • US20030020543A1
    • 2003-01-30
    • US10197145
    • 2002-07-16
    • Anthony Newton
    • H03F003/45
    • H03F3/45085H03F2203/45456H03F2203/45466H03F2203/45498H03F2203/45621
    • A bipolar differential amplifier having first and second transistors (Q1, Q2) and a large third transistor (Q3) sharing a common load resistor (Rt), and DC biasing for biasing the bases of the first, second and third transistors, whereby the first and second transistors have a DC operating current whose value I is related to the common resistor value Rt and the thermal voltage Vt by the expression RtnullVt/2I. In this way the gain of the differential amplifier remains substantially constant over a wide range of the input signal. This produces advantages of: a wide range of linear operation, a relative low bias current may be used, and lack of noise at the central operating point introduced by the large third transistor and the load resistor.
    • 具有共享公共负载电阻(Rt)的第一和第二晶体管(Q1,Q2)和大的第三晶体管(Q3)的双极性差分放大器以及用于偏置第一,第二和第三晶体管的基极的DC偏置,由此第一 并且第二晶体管具有其工作电流I,其值I与公共电阻值Rt和热电压Vt相关,表达式为Rt = Vt / 2I。 以这种方式,差分放大器的增益在输入信号的宽范围内保持基本恒定。 这产生的优点是:宽范围的线性操作,可以使用相对低的偏置电流,并且由大的第三晶体管和负载电阻引入的中心工作点处的噪声不足。
    • 7. 发明授权
    • Arrangement for stabilizing the gain bandwidth product
    • 用于稳定增益带宽积的布置
    • US5912589A
    • 1999-06-15
    • US883007
    • 1997-06-26
    • John Michael KhouryAngelo Rocco MastrocolaRandall Russell Pratt
    • John Michael KhouryAngelo Rocco MastrocolaRandall Russell Pratt
    • H03F3/45
    • H03F3/4508H03F3/45085H03F3/45278H03F2203/45286H03F2203/45456H03F2203/45466H03F2203/45471H03F2203/45476H03F2203/45508
    • A circuit for stabilizing the gain-bandwidth product of analog circuits containing bipolar devices which determine the gm is disclosed. The stabilization circuit is formed to generate a reference current that is proportional to a reference capacitance C.sub.S and the thermal voltage V.sub.T. The reference current is ultimately mirrored (as the bias current) into the bipolar devices which determine the gm within the analog circuit. Since the transconductance gm of a bipolar device can be expressed as collector current, I.sub.C, divided by V.sub.T, the thermal voltage factor of the bias current itself will "cancel" the thermal voltage factor present in the transconductance. The effects related to the remaining variable, the capacitance, will be eliminated as long as the reference capacitance is formed to "track" the analog circuit capacitance by using similar types of capacitance to implement both capacitors and forming both the stabilization circuit and the analog circuit on the same silicon chip. The stabilization circuit can be constructed in modular form and may include a module capable of creating a stabilized RC time constant that is likewise unchanged by variations in temperature or processing.
    • 公开了一种用于稳定包含确定gm的双极器件的模拟电路的增益带宽乘积的电路。 形成稳定电路以产生与参考电容CS和热电压VT成比例的参考电流。 最终将参考电流镜像(作为偏置电流)进入确定模拟电路内的gm的双极型器件。 由于双极器件的跨导gm可以表示为集电极电流(IC)除以VT,因此偏置电流本身的热电压系数将“抵消”跨导中存在的热电压系数。 只要参考电容形成为“跟踪”模拟电路电容,通过使用相似类型的电容来实现两个电容并形成稳定电路和模拟电路两者,就可以消除与剩余变量相关的影响,即电容。 在同一个硅芯片上。 稳定电路可以以模块化形式构造,并且可以包括能够产生稳定的RC时间常数的模块,其通过温度或处理的变化同样不变。
    • 8. 发明授权
    • Low noise, low offset, high speed CMOS differential amplifier
    • 低噪声,低失调,高速CMOS差分放大器
    • US5047665A
    • 1991-09-10
    • US538974
    • 1990-06-15
    • Rodney T. Burt
    • Rodney T. Burt
    • H03F3/45H03M1/06H03M1/12H03M1/46
    • H03F3/45188H03F2203/45456H03F2203/45462H03F2203/45508H03F2203/45652H03F2203/45702
    • A dual successive approximation analog-to-digital converter, including circuitry for generating separate reference voltages for each analog-to-digital converter, is integrated onto a single semiconductor chip. A single successive approximation register including a 19 bit shift register and two 18 bit latches and associated gating circuitry operates to produce two sets of 18 successive approximation numbers, one supplied as successive digital inputs to a CDAC of one of the analog-to-digital converters and the other set of successive approximation numbers being applied as digital inputs to a CDAC of the other analog-to-digital converter. A CMOS comparator includes two high speed, low gain differential amplifier stages, the first including cascode MOSFETs to provide a high power supply rejection. A pair of auto-zeroing capacitors and a pair of auto-zeroing MOSFETs operate on the outputs of the second differential amplifier to reduce input offset voltage, achieving high speed, low noise operation in a small amount of semiconductor chip area. The auto-zeroed output is supplied to the input of a two stage differential amplifier, the outputs of which also are auto-zeroed and applied to a differential CMOS latch, thereby providing a high speed, low noise, low offset CMOS comparator.
    • 包括用于为每个模数转换器产生单独参考电压的电路的双逐次逼近模数转换器被集成到单个半导体芯片上。 包括19位移位寄存器和两个18位锁存器和相关门控电路的单个逐次逼近寄存器操作以产生两组18个逐次逼近数字,一组作为连续的数字输入提供给模数转换器之一的CDAC 并且另一组逐次逼近数字被用作数字输入到另一模数转换器的CDAC。 CMOS比较器包括两个高速,低增益差分放大器级,第一个包括共源共栅MOSFET,以提供高电源抑制。 一对自动归零电容器和一对自动归零MOSFET在第二差分放大器的输出上工作,以减少输入失调电压,实现少量半导体芯片面积的高速度,低噪声运行。 自动归零输出被提供给两级差分放大器的输入,它们的输出也被自动归零并应用于差分CMOS锁存器,从而提供高速,低噪声,低失调的CMOS比较器。