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1. 发明申请

US20160211885A1 Radio Frequency Bitstream Generator and Combiner Providing Image Rejection 有权
标题翻译：射频码流发生器和组合器提供图像抑制
公开(公告)号：US20160211885A1
公开(公告)日：2016-07-21
申请号：US14381019
申请日：2013-03-14
申请人： LSI Corporation
发明人： Donald R. Laturell , Said E. Abdelli , Peter Kiss , James F. MacDonald , Ross S. Wilson
IPC分类号： H04B3/02 , H04B15/00
CPC分类号： H04B3/02 , G06G7/14 , H04B15/00
摘要： A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.
摘要翻译：用于组合模拟信号的电路包括第一和第二比特流发生器和与之相连的定向耦合。第一比特流发生器接收第一模拟信号并产生第一数字比特流作为其功能。第二比特流发生器接收第二模拟信号并产生第二数字比特流作为其功能。第一和第二比特流发生器被配置为保持第一和第二数字比特流之间的九十度的相位差。定向耦合器在第一端口处接收第一数字比特流，并在第二端口接收第二数字比特流。定向耦合器包括端接的第三端口，以及第四端口，其产生指示第一和第二数字位流的组合的第一输出信号，以使图像分量被抑制而不需要滤波。

2. 发明申请

US20160056848A1 SINGLE-SIDEBAND TRANSMITTER USING CLASS-S AMPLIFIER 有权
标题翻译：单级放大器单侧发射机
公开(公告)号：US20160056848A1
公开(公告)日：2016-02-25
申请号：US14380936
申请日：2013-03-15
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , James F. MacDonald , Steven C. Pinault , Ross S. Wilson
IPC分类号： H04B1/04 , H04L27/02
CPC分类号： H04B1/0475 , H03C1/52 , H03C1/60 , H03F3/24 , H04B1/68 , H04B2001/0408 , H04L27/02 , H04L27/06 , H04L27/063
摘要： An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.
摘要翻译： SSB发射机包括数字 - 数字转换器，其产生作为提供给发射机的复合输入信号的函数的第一和第二实信号分量;以及数字希尔伯特变换模块，与数字 - 数字转换器耦合并且可操作以产生第一和第二变换信号作为第一和第二实信号分量的函数。发射机还包括第一和第二比特流发生器，用于分别产生作为第一和第二变换信号的函数的第一和第二模拟信号。发射机包括第一和第二放大器。第一放大器用于产生作为第一模拟信号的函数的第一放大信号。第二放大器用于产生作为第二模拟信号的函数的第二放大信号。模拟混合耦合器与第一和第二放大器连接并且可操作以执行模拟希尔伯特变换。

3. 发明授权

US09078352B2 Low inductance flex bond with low thermal resistance 有权
标题翻译：低电感柔性接合，低热阻
公开(公告)号：US09078352B2
公开(公告)日：2015-07-07
申请号：US13662659
申请日：2012-10-29
申请人： LSI Corporation
发明人： Donald R. Laturell , Said E. Abdelli , Peter Kiss , James F. MacDonald , Ross S. Wilson
IPC分类号： H05K1/00 , H05K3/30 , H05K1/02 , H01L23/498 , H05K3/46
CPC分类号： H05K1/0216 , H01L23/4985 , H01L23/5387 , H01L2224/48472 , H01L2224/49111 , H01L2224/49175 , H01L2924/30107 , H01L2924/3011 , H05K1/028 , H05K3/306 , H05K3/4691 , H05K2201/042 , Y10T29/4913 , H01L2924/00
摘要： A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.
摘要翻译：公开了具有低电感连接的电子电路。电子电路包括接地平面和柔性电路。柔性电路具有大致面向接地平面的第一表面和与第一表面相对的第二表面。柔性电路还具有由其限定的柔性桥。电子电路还包括通信地耦合到柔性电路的第二表面的第一电子设备，通信地耦合到柔性电路的第二表面的第二电子设备，以及限定在柔性电路的第二表面上的至少一个导电迹线并沿柔性桥延伸。所述至少一个导电迹线的一端被配置为用于从所述第一电子器件接收出站电流，并且所述至少一个导电迹线的另一端通过垂直互连接入通信地耦合到所述第二电子器件。

4. 发明申请

US20140266820A1 INTERLEAVED MULTIPATH DIGITAL POWER AMPLIFICATION 有权
公开(公告)号：US20140266820A1
公开(公告)日：2014-09-18
申请号：US14184334
申请日：2014-02-19
申请人： LSI Corporation
发明人： Peter Kiss , Said E. Abdelli , Donald R. Laturell , Ross S. Wilson , James F. MacDonald
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03F3/217 , H03F2200/331 , H03H17/0018 , H03H17/0273 , H03H17/028 , H03M3/30 , H03M3/37 , H03M3/47 , H04L25/02 , H04L27/02
摘要： In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

5. 发明授权

US08824591B2 Digital radio frequency clocking methods 有权
标题翻译：数字射频时钟方式
公开(公告)号：US08824591B2
公开(公告)日：2014-09-02
申请号：US13660520
申请日：2012-10-25
申请人： LSI Corporation
发明人： Ross S. Wilson , Said E. Abdelli , Peter Kiss , Donald R. Laturell , James F. MacDonald
IPC分类号： H04L27/00
CPC分类号： H04J3/0685
摘要： A method and system for synchronous transfer of bitstream data between a power-driver chip and a digital signal processing chip in a digital radio frequency transmit system is disclosed. A master phase-locked-loop located in the power-driver chip is utilized to provide master clocking control for the digital radio frequency transmit system. Furthermore, the clocking method and system is configurable to secure precise carrier frequency positioning of a digitally-generated radio frequency signal based on predetermined chip frequencies unrelated to the carrier frequency, assuring low bitstream phase noise at the output of the power driver chip.
摘要翻译：公开了一种用于在数字射频发射系统中的功率驱动器芯片和数字信号处理芯片之间同步传输比特流数据的方法和系统。位于功率驱动器芯片中的主锁相环被用于为数字射频发射系统提供主时钟控制。此外，时钟方法和系统可配置为基于与载波频率无关的预定码片频率来确保数字产生的射频信号的精确载波频率定位，确保在功率驱动器芯片的输出处的低位流相位噪声。

6. 发明申请

US20140159991A1 SWITCHING POWER AMPLIFIER SYSTEM FOR MULTI-PATH SIGNAL INTERLEAVING 有权
标题翻译：切换功率放大器系统进行多路信号交互
公开(公告)号：US20140159991A1
公开(公告)日：2014-06-12
申请号：US13709743
申请日：2012-12-10
申请人： LSI CORPORATION
发明人： Peter Kiss , Said E. Abdelli , Kameran Azadet , Donald R. Laturell , James F. MacDonald , Ross S. Wilson
IPC分类号： H03F1/00 , H03H11/00 , H01Q23/00
CPC分类号： H03H11/00 , H03F3/2175 , H03F3/24 , H03M3/50
摘要： A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.
摘要翻译：一种用于多径信号交织的开关功率放大器包括：信号分配器，被配置为将来自数字源的多位源信号分离成多个多位信号;一个或多个分数延迟滤波器，被配置为延迟一个或多个信号所述多个信号经过选定的时间，多个比特流转换器，每个比特流转换器被配置为接收所述多比特信号中的一个，每个比特流转换器还被配置为基于所述多比特信号生成单比特信号接收的多位信号，多个开关功率放大器，每个开关功率放大器被配置为从位流转换器之一接收单位信号;以及交织器，被配置为通过交织两个或多个输出开关功率放大器，其中交织器的交错输出的采样频率大于所选择的多位源信号的采样频率。

7. 发明授权

US09325284B2 Radio frequency composite Class-S power amplifier having discrete power control 有权
标题翻译：具有离散功率控制的射频复合S类功率放大器
公开(公告)号：US09325284B2
公开(公告)日：2016-04-26
申请号：US14380915
申请日：2013-02-02
申请人： LSI Corporation
发明人： Ross S. Wilson , Said E. Abdelli , Peter Kiss , Donald R. Laturell , James F. MacDonald
IPC分类号： H03F3/217 , H03F1/02 , H03F1/32 , H03F1/56 , H03F3/195 , H03F3/21 , H03F3/24 , H03F3/45 , H03F3/72 , H03F3/193
CPC分类号： H03F3/2171 , H03F1/0222 , H03F1/0277 , H03F1/3241 , H03F1/56 , H03F3/193 , H03F3/195 , H03F3/211 , H03F3/217 , H03F3/2175 , H03F3/245 , H03F3/45179 , H03F3/72 , H03F2200/336 , H03F2200/387 , H03F2200/408 , H03F2200/411 , H03F2200/451 , H03F2200/504 , H03F2201/3212 , H03F2201/3233 , H03F2203/45638 , H03F2203/45731 , H03F2203/7215 , H03F2203/7236
摘要： A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal. A method of providing digitally selectable amplification includes steps of: selectively coupling a digital bitstream to a plurality of channels in the amplifier; amplifying the digital bitstream to provide an amplified signal associated with a corresponding one of the channels; filtering amplified signals associated with the channels to provide corresponding filtered signals; and combining the filtered signals to generate a composite output signal.
摘要翻译：提供数字可选择放大的复合放大器包括多个通道和组合器。每个通道包括数字可控选择器，S类功率放大器和带通滤波器。数字可控选择器选择性地将数字比特流耦合到放大器。放大器接收数字比特流并提供放大的信号。带通滤波器产生作为放大信号的函数的滤波信号。组合器将由信道提供的滤波信号耦合以形成复合输出信号。提供数字可选择放大的方法包括以下步骤：选择性地将数字比特流耦合到放大器中的多个通道; 放大数字比特流以提供与相应的一个信道相关联的放大信号; 滤波与信道相关联的放大信号以提供对应的滤波信号; 以及组合经滤波的信号以产生复合输出信号。

8. 发明申请

US20140191801A1 BICMOS GATE DRIVER FOR CLASS-S RADIO FREQUENCY POWER AMPLIFIER 有权
标题翻译： BICMOS门控级无线射频功率放大器
公开(公告)号：US20140191801A1
公开(公告)日：2014-07-10
申请号：US13736442
申请日：2013-01-08
申请人： LSI CORPORATION
发明人： Ross S. Wilson , Said E. Abdelli , Peter Kiss , Donald R. Laturell , Kameran Azadet , James F. MacDonald
IPC分类号： H03F3/217 , H03F3/193
CPC分类号： H03F3/2171 , H03F3/193 , H03F3/195 , H03F3/245 , H03F3/305 , H03F3/45179 , H03F3/45183 , H03F2200/78 , H03F2203/45394 , H03F2203/45456 , H03F2203/45631 , H03F2203/45702
摘要： The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital Class-S Radio Frequency Power Amplifier (RF-PA). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, Viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the Class-S RF-PA. The drive circuit provides a high slew-rate, large-swing, quasi-digital gate drive circuit to drive the significant gate capacitance of the RF-PA with sufficient rise times. A combination of bipolar transistor current switches and cascoded CMOS devices is employed to attain requisite performance. For example, the driving circuit is well suited for use with Class-S RF-PAs used in wireless communication systems.
摘要翻译：本发明可以体现在用于驱动数字S类射频功率放大器（RF-PA）的栅电极的再同步推挽驱动电路中。从比特流发生器（例如，Σ-Δ调制器，基于维特比的最佳位模式调制器Σ-Δ或其它合适的调制器）接收的二进制比特流被重新同步到低抖动主时钟，上升，高挥发互补数字信号驱动S-S RF-PA的门。驱动电路提供高压摆率，大摆幅，准数字栅极驱动电路，以足够的上升时间驱动RF-PA的显着栅极电容。采用双极晶体管电流开关和级联CMOS器件的组合来实现必要的性能。例如，驱动电路非常适用于无线通信系统中使用的S类RF-PA。

9. 发明申请

US20140184323A1 Hybrid Digital/Analog Power Amplifier 有权
标题翻译：混合数字/模拟功率放大器
公开(公告)号：US20140184323A1
公开(公告)日：2014-07-03
申请号：US13729231
申请日：2012-12-28
申请人： LSI CORPORATION
发明人： Ross S. Wilson , Said E. Abdelli , Peter Kiss , Kameran Azadet , Donald R. Laturell , James F. MacDonald
IPC分类号： H03F3/38
CPC分类号： H03F3/38 , H03F3/189 , H03F3/217
摘要： The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.
摘要翻译：本发明可以体现在使用混合模拟/数字RF架构的射频功率放大器（RF-PA）预驱动电路中，所述混合模拟/数字RF架构包括重新同步的数模转换器，以驱动适于驱动标准高功率放大器的高效大功率输出级（HPA）输出设备。混合模拟/数字RF架构保留了传统S类架构中高数字内容集成的优点，同时放松了对输出晶体管和位流发生器的性能要求。所得到的预驱动电路将数字设计的VLSI集成优势与模拟设计特有的任意输出功率电平的可扩展性相结合。混合模拟/数字驱动电路非常适用于无线通信系统中使用的模拟和Class-S HPA，例如Doherty型HPA。

10. 发明申请

US20140119470A1 Digital Radio Frequency Clocking Methods 有权
标题翻译：数字射频时钟方法
公开(公告)号：US20140119470A1
公开(公告)日：2014-05-01
申请号：US13660520
申请日：2012-10-25
申请人： LSI CORPORATION
发明人： Ross S. Wilson , Said E. Abdelli , Peter Kiss , Donald R. Laturell , James F. MacDonald
IPC分类号： H04L27/00
CPC分类号： H04J3/0685
摘要： A method and system for synchronous transfer of bitstream data between a power-driver chip and a digital signal processing chip in a digital radio frequency transmit system is disclosed. A master phase-locked-loop located in the power-driver chip is utilized to provide master clocking control for the digital radio frequency transmit system. Furthermore, the clocking method and system is configurable to secure precise carrier frequency positioning of a digitally-generated radio frequency signal based on predetermined chip frequencies unrelated to the carrier frequency, assuring low bitstream phase noise at the output of the power driver chip.
摘要翻译：公开了一种用于在数字射频发射系统中的功率驱动器芯片和数字信号处理芯片之间同步传输比特流数据的方法和系统。位于功率驱动器芯片中的主锁相环被用于为数字射频发射系统提供主时钟控制。此外，时钟方法和系统可配置为基于与载波频率无关的预定码片频率来确保数字产生的射频信号的精确载波频率定位，确保在功率驱动器芯片的输出处的低位流相位噪声。

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