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1. 发明授权

US09929703B1 Amplifier with configurable final output stage 有权
公开(公告)号：US09929703B1
公开(公告)日：2018-03-27
申请号：US15277465
申请日：2016-09-27
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： Xin Zhao , Tejasvi Das , Xiaofan Fei , Alan Mark Morton
IPC分类号： H03F3/38 , H03F3/217 , H03F3/187 , H03F1/34
CPC分类号： H03F3/2171 , H03F1/32 , H03F1/342 , H03F3/181 , H03F3/187 , H03F3/217 , H03F3/2173 , H03F3/38 , H03F3/72 , H03F2200/345 , H03F2200/351
摘要： An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.

2. 发明申请

US20170363693A1 HIGH BANDWIDTH HALL SENSOR 审中-公开
公开(公告)号：US20170363693A1
公开(公告)日：2017-12-21
申请号：US15186383
申请日：2016-06-17
申请人： Texas Instruments Incorporated
发明人： Arup Polley , Srinath Ramaswamy , Baher S. Haroun , Rajarshi Mukhopadhyay
IPC分类号： G01R33/00 , G01R33/07
CPC分类号： G01R33/0029 , G01R33/075 , H03F3/38 , H03F3/45995
摘要： A high bandwidth Hall sensor includes a high bandwidth path and a low bandwidth path. The relatively high offset (from sensor offset) of the high bandwidth path is estimated using a relatively low offset generated by the low bandwidth path. The relatively high offset of the high bandwidth path is substantially reduced by combining the output of the high bandwidth path with the output of the low bandwidth path to generate a high bandwidth, low offset output. The offset can be further reduced by including transimpedance amplifiers in the high bandwidth sensors to optimize the frequency response of high bandwidth Hall sensor.

3. 发明申请

US20170054416A1 CLASS-D AUDIO AMPLIFIER 有权
标题翻译： CLASS-D音频放大器
公开(公告)号：US20170054416A1
公开(公告)日：2017-02-23
申请号：US15240341
申请日：2016-08-18
申请人： Silergy Semiconductor Technology (Hangzhou) Ltd.
发明人： Huaping Zhu , Hejinsheng Cao , Qichang Wu , Zhenguo Sun
IPC分类号： H03F1/26 , H04R3/02 , H03F1/34 , H03F3/187 , H03F3/213
CPC分类号： H04R3/02 , H03F1/305 , H03F1/342 , H03F3/185 , H03F3/187 , H03F3/213 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/38 , H03F3/45475 , H03F2200/03 , H03F2200/351 , H03F2200/432 , H03F2203/45512 , H03F2203/45528 , H03F2203/45534 , H03F2203/45536 , H03F2203/45594 , H03F2203/45631 , H03F2203/45634 , H03F2203/45702 , H03G3/348 , H04R2430/01
摘要： The present disclosure relates to a class-D audio amplifier. When the system is powered on, an auxiliary power amplifier and an auxiliary feedback circuit constitute an auxiliary close loop so that a control loop is established in advance. The auxiliary close loop is disconnected after various circuit modules reach their steady operation points, and the system operates at a normal state. A soft start circuit is provided for suppressing noise which occurs when the system is powered on. Thus, the class-D audio amplifier suppresses POP noise at an output terminal when the system is powered on.
摘要翻译：本公开涉及D类音频放大器。当系统通电时，辅助功率放大器和辅助反馈电路构成辅助闭环，提前建立控制回路。各种电路模块到达稳定运行点后，辅助闭环断开，系统工作在正常状态。提供软启动电路，用于抑制当系统通电时发生的噪声。因此，当系统通电时，D类音频放大器抑制输出端口的POP噪声。

4. 发明授权

US09065398B2 Amplifying circuit capable of suppressing spikes of an audio signal 有权
标题翻译：能抑制音频信号尖峰的放大电路
公开(公告)号：US09065398B2
公开(公告)日：2015-06-23
申请号：US13671524
申请日：2012-11-07
申请人： Yung-Ming Lee , Ming-Chung Li
发明人： Yung-Ming Lee , Ming-Chung Li
IPC分类号： H03F1/34 , H03F3/217 , H03F3/38 , H03F1/02 , H03F1/52 , H03F3/185 , H03F1/32 , H03K7/08
CPC分类号： H03F1/342 , H03F1/523 , H03F3/217 , H03F3/2171 , H03F3/38
摘要： An amplifying circuit capable of suppressing spikes of an audio signal includes an integration module, a comparison module, an output module, a feedback module, and a limiting module. The integration module is used for receiving an input signal and generating a first voltage signal corresponding to the input signal. The comparison module is coupled to the integration module for receiving the first voltage signal and a reference signal, and generating a comparison signal. The output module is coupled to the comparison module for generating an audio signal according to the comparison signal. The feedback module is coupled between the output module and the integration module for feeding back an output signal to the integration module. The limiting module is coupled between the feedback module and the integration module for limiting the comparison signal to be within a predetermined range.
摘要翻译：能够抑制音频信号尖峰的放大电路包括集成模块，比较模块，输出模块，反馈模块和限制模块。积分模块用于接收输入信号并产生对应于输入信号的第一电压信号。比较模块耦合到积分模块，用于接收第一电压信号和参考信号，并产生比较信号。输出模块耦合到比较模块，用于根据比较信号产生音频信号。反馈模块耦合在输出模块和集成模块之间，用于将输出信号反馈给集成模块。限制模块耦合在反馈模块和积分模块之间，用于将比较信号限制在预定范围内。

5. 发明授权

US08773196B2 Resource pooling amplifier 有权
标题翻译：资源池放大器
公开(公告)号：US08773196B2
公开(公告)日：2014-07-08
申请号：US13626672
申请日：2012-09-25
申请人： Cary L. Delano
发明人： Cary L. Delano
IPC分类号： H03F3/38 , H03F3/217
CPC分类号： H03F3/38 , H03F3/005 , H03F3/181 , H03F3/217 , H03F3/45928 , Y10T307/76
摘要： A new type of amplifier, herein designated a resource pooling amplifier, involves extended usage of one or more inductors that is implemented by sharing. The sharing is either by switching the inductor or inductors among more than one load terminal at the same time (e.g., a bridged configuration or two different loads terminals with different polarity requirements) or by using the inductor or inductors for more than one purpose at different times. The inductor or inductors may be time shared such as by allocating different phases of a clock. The inductor or inductors may also be shared by monitoring load requirements and using the inductor or inductors only when needed (leaving other inductor cycles for other loads). In addition, inductor sharing may be implemented during different application requirements such as if two or more loads are not needed at the same time in a system. These types of sharing may be combined.
摘要翻译：一种新型放大器（这里称为资源池放大器）涉及通过共享实现的一个或多个电感器的扩展使用。共享是通过同时在多个负载端子之间切换电感器或电感器（例如，桥接配置或具有不同极性要求的两个不同负载端子），或者通过在不同的方式使用电感器或电感器用于多于一个目的次电感器或电感器可以是时间共享的，例如通过分配时钟的不同相位。电感器或电感器也可以通过监视负载要求并仅在需要时使用电感器或电感器（为其他负载留下其他电感器周期）来共享。此外，可以在不同的应用需求期间实现电感器共享，例如在系统中不需要两个或更多个负载的同时。这些类型的共享可以组合。

6. 发明申请

US20140184323A1 Hybrid Digital/Analog Power Amplifier 有权
标题翻译：混合数字/模拟功率放大器
公开(公告)号：US20140184323A1
公开(公告)日：2014-07-03
申请号：US13729231
申请日：2012-12-28
申请人： LSI CORPORATION
发明人： Ross S. Wilson , Said E. Abdelli , Peter Kiss , Kameran Azadet , Donald R. Laturell , James F. MacDonald
IPC分类号： H03F3/38
CPC分类号： H03F3/38 , H03F3/189 , H03F3/217
摘要： The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.
摘要翻译：本发明可以体现在使用混合模拟/数字RF架构的射频功率放大器（RF-PA）预驱动电路中，所述混合模拟/数字RF架构包括重新同步的数模转换器，以驱动适于驱动标准高功率放大器的高效大功率输出级（HPA）输出设备。混合模拟/数字RF架构保留了传统S类架构中高数字内容集成的优点，同时放松了对输出晶体管和位流发生器的性能要求。所得到的预驱动电路将数字设计的VLSI集成优势与模拟设计特有的任意输出功率电平的可扩展性相结合。混合模拟/数字驱动电路非常适用于无线通信系统中使用的模拟和Class-S HPA，例如Doherty型HPA。

7. 发明授权

US08736362B2 Pulse width modulation signal generating circuit and amplifier circuit with beat frequency cancellation circuit 有权
标题翻译：脉宽调制信号发生电路和具有拍频消除电路的放大电路
公开(公告)号：US08736362B2
公开(公告)日：2014-05-27
申请号：US13414218
申请日：2012-03-07
申请人： Chun-Jen Huang , Jiann-Chyi Rau , Hsin-Hung Wang
发明人： Chun-Jen Huang , Jiann-Chyi Rau , Hsin-Hung Wang
IPC分类号： H03F3/38
CPC分类号： H03F3/38 , H03F1/32 , H03F3/2173 , H03F3/68 , H03F2200/351
摘要： A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.
摘要翻译：用于放大器的拍频消除电路包括连接在放大器的两个信号处理路径之间的耦合装置，用于补偿信号处理路径之间的输出信号的拍频效果。

8. 发明申请

US20140022017A1 INTEGRATOR INPUT ERROR CORRECTION CIRCUIT AND CIRCUIT METHOD 有权
标题翻译：集成输入错误校正电路和电路方法
公开(公告)号：US20140022017A1
公开(公告)日：2014-01-23
申请号：US14039076
申请日：2013-09-27
申请人： Marvell World Trade Ltd.
发明人： Sasan Cyrusian
IPC分类号： H03F3/26
CPC分类号： H03F3/38 , H03F3/217 , H03F3/26
摘要： A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current.
摘要翻译：电路包括第一放大器和第二放大器，其中第一放大器被配置为在第一放大器的第一输入处接收输入电流，并且第一op-mp的输出被配置为驱动第二放大器的第一输入。电路还包括选择性地耦合到第二放大器的第一输入的上拉电流源，以及选择性地耦合到第二放大器的第一输入的下拉电流源。如果输入电流的绝对值大于预定义的阈值电流：i）上拉电流源被配置成驱动电流进入第二放大器的第一输入端用于输入电流的第一极性，以及ii）下拉电流源被配置为从输入电流的第二极性吸收来自第二放大器的第一输入端的电流。

9. 发明申请

US20120229207A1 PULSE WIDTH MODULATION SIGNAL GENERATING CIRCUIT AND AMPLIFIER CIRCUIT WITH BEAT FREQUENCY CANCELLATION CIRCUIT 有权
标题翻译：脉冲宽度调制信号产生电路和放大器电路与BEAT频率取消电路
公开(公告)号：US20120229207A1
公开(公告)日：2012-09-13
申请号：US13414218
申请日：2012-03-07
申请人： Chun-Jen HUANG , Jiann-Chyi RAU , Hsin-Hung WANG
发明人： Chun-Jen HUANG , Jiann-Chyi RAU , Hsin-Hung WANG
IPC分类号： H03F3/68
CPC分类号： H03F3/38 , H03F1/32 , H03F3/2173 , H03F3/68 , H03F2200/351
摘要： A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths.
摘要翻译：用于放大器的拍频消除电路包括连接在放大器的两个信号处理路径之间的耦合装置，用于补偿信号处理路径之间的输出信号的拍频效果。

10. 发明申请

US20120139612A1 INTEGRATOR INPUT ERROR CORRECTION CIRCUIT AND CIRCUIT METHOD 失效
标题翻译：集成输入错误校正电路和电路方法
公开(公告)号：US20120139612A1
公开(公告)日：2012-06-07
申请号：US13313491
申请日：2011-12-07
申请人： Sasan Cyrusian
发明人： Sasan Cyrusian
IPC分类号： G06G7/18
CPC分类号： H03F3/38 , H03F3/217 , H03F3/26
摘要： A circuit includes a first amplifier and a second amplifier, wherein first amplifier is configured to receive an input current at a first input of the first amplifier, and an output of the first op-mp is configured to drive a first input of the second amplifier. The circuit further includes a pull-up current source selectively coupled to the first input of the second amplifier, and a pull-down current source selectively coupled to the first input of the second amplifier. If the absolute value of the input current is larger than a predefined threshold current: i) the pull-up current source is configured to drive current into the first input of the second amplifier for a first polarity of the input current, and ii) the pull-down current source is configured to sink current from the first input of the second amplifier for a second polarity of the input current.
摘要翻译：电路包括第一放大器和第二放大器，其中第一放大器被配置为在第一放大器的第一输入处接收输入电流，并且第一op-mp的输出被配置为驱动第二放大器的第一输入。电路还包括选择性地耦合到第二放大器的第一输入的上拉电流源，以及选择性地耦合到第二放大器的第一输入的下拉电流源。如果输入电流的绝对值大于预定义的阈值电流：i）上拉电流源被配置成驱动电流进入第二放大器的第一输入端用于输入电流的第一极性，以及ii）下拉电流源被配置为从输入电流的第二极性吸收来自第二放大器的第一输入端的电流。

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