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1. 发明申请

US20140317163A1 Vector Processor Having Instruction Set With Sliding Window Non-Linear Convolutional Function 有权
标题翻译：具有滑动窗口非线性卷积函数的指令集的向量处理器
公开(公告)号：US20140317163A1
公开(公告)日：2014-10-23
申请号：US14168615
申请日：2014-01-30
申请人： LSI Corporation
发明人： Kameran Azadet , Joseph Williams , Meng-Lin Yu
IPC分类号： G06F17/15
CPC分类号： H04L5/1461 , G06F9/30036 , G06F17/15 , G06F17/50 , G06F17/5009 , H04B1/0475 , H04B1/525 , H04B1/62 , H04B2001/0425 , H04J11/004 , H04L1/0043 , H04L25/03012 , H04L25/03343 , H04L25/08 , H04L27/367 , H04L27/368
摘要： A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function.
摘要翻译：提供具有具有滑动窗非线性卷积函数的指令集的处理器。处理器获得对多个输入延迟信号样本执行非线性卷积函数的软件指令。响应于用于非线性卷积函数的软件指令，处理器生成两个或更多个输入延迟信号样本的加权和，其中加权和包括被定义为一个或多个非线性卷积的和的多个可变系数，输入延迟信号采样幅度的线性函数; 并重复所述生成步骤，用于输入延迟信号采样的至少一个时移版本，以计算多个连续输出。用于非线性卷积函数的软件指令可选地是处理器的指令集的一部分。非线性卷积函数可以对具有存储器的非线性系统进行建模，例如功率放大器模型和/或数字预失真功能。

2. 发明授权

US08831133B2 Recursive digital pre-distortion (DPD) 有权
标题翻译：递归数字预失真（DPD）
公开(公告)号：US08831133B2
公开(公告)日：2014-09-09
申请号：US13661357
申请日：2012-10-26
申请人： LSI Corporation
发明人： Kameran Azadet , Albert Molina
IPC分类号： H04L27/00 , H04L27/233 , H04L25/03 , H04B1/04 , H04L1/00 , G06F5/01 , H04L25/02 , G06F9/30 , H03M3/00 , H04B1/62
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： Recursive digital pre-distortion (DPD) techniques are provided. Digital pre-distortion is performed by applying a signal to a recursive system to generate a state vector; providing the state vector as a feedback value to the recursive non-linear system; and applying the state vector to a second function to generate an output signal, wherein at least one of the recursive system and the second function comprise a non-linear function. The recursive non-linear system can be initialized to a known initial value. The recursive system is defined by a system of non-linear differential equations.
摘要翻译：提供递归数字预失真（DPD）技术。通过向递归系统施加信号以产生状态向量来执行数字预失真; 将状态向量作为反馈值提供给递归非线性系统; 以及将所述状态向量应用于第二函数以产生输出信号，其中所述递归系统和所述第二函数中的至少一个包括非线性函数。递归非线性系统可以初始化为已知的初始值。递归系统由非线性微分方程系统定义。

3. 发明申请

US20140064417A1 Direct Digital Synthesis Of Signals Using Maximum Likelihood Bit-Stream Encoding 有权
标题翻译：使用最大似然比特流编码的信号的直接数字合成
公开(公告)号：US20140064417A1
公开(公告)日：2014-03-06
申请号：US13701369
申请日：2012-10-26
申请人： LSI Corporation
发明人： Kameran Azadet
IPC分类号： H04L27/233
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized by performing maximum likelihood sequence estimation on the digital RF input signal to produce a digital stream, such that after filtering by a prototype filter the produced digital stream produces a substantially minimum error. The substantially minimum error comprises a difference between a digital output of the prototype filter and the digital RF input signal. The digital stream is substantially equal to the input digital RF signal. The digital stream can be applied to an analog restitution filter, and the output of the analog restitution filter comprises an analog RF signal that approximates the digital RF input signal.
摘要翻译：提供了使用最大似然序列估计直接合成RF信号的方法和装置。通过对数字RF输入信号执行最大似然序列估计来合成RF数字RF输入信号以产生数字流，使得在通过原型滤波器滤波之后，所产生的数字流产生基本上最小的误差。基本上最小的误差包括原型滤波器的数字输出和数字RF输入信号之间的差异。数字流基本上等于输入的数字RF信号。数字流可以应用于模拟恢复滤波器，并且模拟恢复滤波器的输出包括近似数字RF输入信号的模拟RF信号。

4. 发明授权

US08995521B2 Method and apparatus for high density pulse density modulation 有权
标题翻译：用于高密度脉冲密度调制的方法和装置
公开(公告)号：US08995521B2
公开(公告)日：2015-03-31
申请号：US13663534
申请日：2012-10-30
申请人： LSI Corporation
发明人： Donald R. Laturell , Said E. Abdelli , Peter Kiss , James F. MacDonald , Ross S. Wilson , Kameran Azadet
IPC分类号： H03K7/04 , H04L27/04 , H03M5/04 , H03G11/00
CPC分类号： H04L27/04 , H03F3/217 , H03F3/24 , H03F3/60 , H03G11/002 , H03M5/04
摘要： A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.
摘要翻译：公开了一种用于高密度脉冲密度调制的方法和系统。根据本公开，使用互补的一对非线性函数将调制功能分为两个频带限制流。更具体地，一个比特流定义包含原始功能的峰值，而另一个比特流包含原始比特流的软限幅版本。比特流被施加到一对开关放大器，并且可以再次组合比特流以重建原始功能。根据本公开的方法限制了实现更高输出功率所需的输入功率量，降低了工作电压并提高了功率放大器的效率。

5. 发明授权

US08908798B2 Hybrid digital/analog power amplifier 有权
标题翻译：混合数字/模拟功率放大器
公开(公告)号：US08908798B2
公开(公告)日：2014-12-09
申请号：US13729231
申请日：2012-12-28
申请人： LSI Corporation
发明人： Ross S. Wilson , Said E. Abdelli , Peter Kiss , Kameran Azadet , Donald R. Laturell , James F. MacDonald
IPC分类号： H04L27/00 , H03F3/38 , H03F3/189 , H03F3/217
CPC分类号： H03F3/38 , H03F3/189 , H03F3/217
摘要： The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.
摘要翻译：本发明可以体现在使用混合模拟/数字RF架构的射频功率放大器（RF-PA）预驱动电路中，所述混合模拟/数字RF架构包括重新同步的数模转换器，以驱动适于驱动标准高功率放大器的高效大功率输出级（HPA）输出设备。混合模拟/数字RF架构保留了传统S类架构中高数字内容集成的优点，同时放松了对输出晶体管和位流发生器的性能要求。所得到的预驱动电路将数字设计的VLSI集成优势与模拟设计特有的任意输出功率电平的可扩展性相结合。混合模拟/数字驱动电路非常适用于无线通信系统中使用的模拟和Class-S HPA，例如Doherty型HPA。

6. 发明申请

US20140317376A1 Digital Processor Having Instruction Set with Complex Angle Function 有权
标题翻译：具有复角函数的指令集的数字处理器
公开(公告)号：US20140317376A1
公开(公告)日：2014-10-23
申请号：US14255491
申请日：2014-04-17
申请人： LSI Corporation
发明人： Kameran Azadet
IPC分类号： G06F9/30
CPC分类号： H04L5/1461 , G06F9/30036 , G06F17/15 , G06F17/50 , G06F17/5009 , H04B1/0475 , H04B1/525 , H04B1/62 , H04B2001/0425 , H04J11/004 , H04L1/0043 , H04L25/03012 , H04L25/03343 , H04L25/08 , H04L27/367 , H04L27/368
摘要： A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input; in response to at least one of the complex angle software instructions, performing the following steps: invoking at least one complex angle functional unit that implements the one or more complex angle software instructions to apply the complex angle function to the input value, x; and generating an output corresponding to the complex angle of the input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of the digital processor, wherein the complex angle software instruction is part of an instruction set of the digital signal processor. Multiplication operations optionally employ one or more multipliers of the MAC unit of the digital processor.
摘要翻译：提供数字处理器，例如矢量处理器或标量处理器，其具有具有复角函数的指令集。通过获得具有输入值x的一个或多个复杂角软件指令作为输入，对输入值x评估复角度; 响应于所述复杂角度软件指令中的至少一个，执行以下步骤：调用实现所述一个或多个复杂角度软件指令的至少一个复角函数单元以将所述复角函数应用于所述输入值x; 以及使用所述数字处理器的乘法累积（MAC）单元的一个或多个乘法器生成与所述输入值x的复角相对应的输出，其中所述复合角软件指令是所述数字信号的指令集的一部分处理器。乘法运算可选地采用数字处理器的MAC单元的一个或多个乘法器。

7. 发明申请

US20140313946A1 Non-Linear Interference Cancellation For Wireless Transceivers 有权
标题翻译：无线收发器的非线性干扰消除
公开(公告)号：US20140313946A1
公开(公告)日：2014-10-23
申请号：US14230635
申请日：2014-03-31
申请人： LSI Corporation
发明人： Kameran Azadet
IPC分类号： H04L5/14 , H04L25/08
CPC分类号： H04L5/1461 , G06F9/30036 , G06F17/15 , G06F17/50 , G06F17/5009 , H04B1/0475 , H04B1/525 , H04B1/62 , H04B2001/0425 , H04J11/004 , H04L1/0043 , H04L25/03012 , H04L25/03343 , H04L25/08 , H04L27/367 , H04L27/368
摘要： Non-linear interference cancellation techniques are provided for wireless transceivers. Non-linear reduction of interference of a transmit signal on a received signal in a transceiver device, comprises applying the transmit signal to a first non-linear system; applying the received signal to a second non-linear system; and subtracting an output of the first non-linear system output from an output of second non-linear system output to produce an interference mitigated received signal. The first non-linear system and/or the second non-linear system can be to implemented using one or more of a Volterra series and a Generalized Memory Polynomial Model. System parameters of the first non-linear system and/or the second non-linear system are adapted to reduce a power of the interference mitigated received signal.
摘要翻译：为无线收发器提供非线性干扰消除技术。发射信号对收发器设备中的接收信号的干扰的非线性减小包括将发射信号应用于第一非线性系统; 将接收的信号应用于第二非线性系统; 以及从第二非线性系统输出的输出中减去输出的第一非线性系统的输出以产生干扰减轻的接收信号。第一非线性系统和/或第二非线性系统可以使用Volterra系列和广义存储器多项式模型中的一个或多个实现。第一非线性系统和/或第二非线性系统的系统参数适于减小干扰减轻的接收信号的功率。

8. 发明申请

US20140119427A1 Method and Apparatus for High Density Pulse Density Modulation 有权
标题翻译：高密度脉冲密度调制方法与装置
公开(公告)号：US20140119427A1
公开(公告)日：2014-05-01
申请号：US13663534
申请日：2012-10-30
申请人： LSI CORPORATION
发明人： Donald R. Laturell , Said E. Abdelli , Peter Kiss , James F. MacDonald , Ross S. Wilson , Kameran Azadet
IPC分类号： H04L27/04
CPC分类号： H04L27/04 , H03F3/217 , H03F3/24 , H03F3/60 , H03G11/002 , H03M5/04
摘要： A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.
摘要翻译：公开了一种用于高密度脉冲密度调制的方法和系统。根据本公开，使用互补的一对非线性函数将调制功能分为两个频带限制流。更具体地，一个比特流定义包含原始功能的峰值，而另一个比特流包含原始比特流的软限幅版本。比特流被施加到一对开关放大器，并且可以再次组合比特流以重建原始功能。根据本公开的方法限制了实现更高输出功率所需的输入功率量，降低了工作电压并提高了功率放大器的效率。

9. 发明申请

US20140086356A1 Software Digital Front End (SoftDFE) Signal Processing 有权
标题翻译：软件数字前端（SoftDFE）信号处理
公开(公告)号：US20140086356A1
公开(公告)日：2014-03-27
申请号：US13701374
申请日：2012-10-26
申请人： LSI Corporation
发明人： Kameran Azadet , Chengzhou Li , Albert Molina , Joseph H. Othmer , Steven C. Pinault , Meng-Lin Yu , Joseph Willimas , Ramon Sanchez Perez , Jian-Guo Chen
IPC分类号： H04L25/02
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.
摘要翻译：提供软件数字前端（SoftDFE）信号处理技术。通过在处理器上执行一个或多个专用指令对信号执行一个或多个数字前端（DFE）功能，对软件中的信号执行一个或多个数字前端（DFE）功能，其中处理器具有指令由线性和非线性指令中的一个或多个组成。可选地形成由多个数据样本组成的样本块，并且在样本块上执行数字前端（DFE）功能。专门的指令可以包括向量卷积函数，复指数函数，xk函数，向量比较指令，向量max（）指令，向量乘法指令，向量加法指令，向量sqrt（）指令，向量 1 / x指令和用户定义的非线性指令。

10. 发明申请

US20130114761A1 MULTI-STAGE CREST FACTOR REDUCTION (CFR) FOR MULTI-CHANNEL MULTI-STANDARD RADIO 有权
标题翻译：用于多通道多标准无线电的多阶段检测因子减少（CFR）
公开(公告)号：US20130114761A1
公开(公告)日：2013-05-09
申请号：US13661351
申请日：2012-10-26
申请人： LSI Corporation
发明人： Kameran Azadet , Albert Molina
IPC分类号： H04B1/04
CPC分类号： G06F9/3001 , G06F5/01 , G06F9/30036 , G06F17/15 , H03F1/0288 , H03F1/3241 , H03F1/3258 , H03F3/189 , H03F3/24 , H03F2200/336 , H03F2201/3209 , H03F2201/3212 , H03F2201/3224 , H03F2201/3233 , H03H17/06 , H03M3/30 , H04B1/0003 , H04B1/0475 , H04B1/62 , H04B2001/0408 , H04L1/0054 , H04L25/02 , H04L25/03 , H04L25/03178 , H04L25/03216 , H04L25/4917 , H04L27/2334
摘要： Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method comprises applying one or more data samples associated with at least one channel of a first technology type to a first individual crest factor reduction block; applying one or more data samples associated with at least one channel of a second technology type to a second individual crest factor reduction block; aggregating outputs of the first and second individual crest factor reduction blocks to generate an aggregated output; and applying the aggregated output to a composite crest factor reduction block. The individual crest factor reduction blocks can be implemented using a sampling rate appropriate for the corresponding technology type. The composite crest factor reduction block operates at a higher sampling rate than the individual crest factor reduction blocks.
摘要翻译：为多通道多标准无线电（MSR）提供多级波峰因数降低（CFR）技术。多级波峰因数降低方法包括将与第一技术类型的至少一个信道相关联的一个或多个数据样本应用于第一单独波峰因数减少块; 将与第二技术类型的至少一个信道相关联的一个或多个数据样本应用于第二单独波峰因子减小块; 聚合第一和第二单独波峰因子减小块的输出以生成聚合输出; 并将聚合输出应用于复合波峰因数减少块。可以使用适合于相应技术类型的采样率来实现各个波峰因数减小块。复合波峰因数降低块以比单个波峰因数减小块更高的采样速率运行。

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