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1. 发明授权

US09450585B2 Selecting four signals from sixteen inputs 有权
标题翻译：从十六个输入中选择四个信号
公开(公告)号：US09450585B2
公开(公告)日：2016-09-20
申请号：US13449687
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17744
摘要： An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.
摘要翻译：一种用于从设备中的多个y信号中选择多个输入信号的装置具有具有多个n至1个多路复用器的交换矩阵，其中每个n至1多路复用器被分配给y信号的n个的不同输入集合其中n至1个多路复用器中的每一个的每组输入信号的小于n个输入信号的子集也是另一n到1个多路复用器的输入信号的子集。

2. 发明授权

US08710863B2 Configurable logic cells 有权
标题翻译：可配置的逻辑单元
公开(公告)号：US08710863B2
公开(公告)日：2014-04-29
申请号：US13449993
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F15/7871 , H03K19/177 , H03K19/17708
摘要： A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.
摘要翻译：处理器包括一个RISC CPU内核; 以及包括一个或多个可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为允许实时软件访问处理器的内部配置和信号路径。可配置逻辑单元外设可能具有实时配置控制。

3. 发明申请

US20120271968A1 LOGIC DEVICE FOR COMBINING VARIOUS INTERRUPT SOURCES INTO A SINGLE INTERRUPT SOURCE AND VARIOUS SIGNAL SOURCES TO CONTROL DRIVE STRENGTH 审中-公开
标题翻译：用于将各种中断源组合到单个中断源和各种信号源以控制驱动强度的逻辑设备
公开(公告)号：US20120271968A1
公开(公告)日：2012-10-25
申请号：US13450079
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： G06F13/14
CPC分类号： H03K19/17712 , H03K19/17708
摘要： A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.
摘要翻译：处理器包括RISC CPU内核和包括可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为将多个输入组合成单个输出。可配置逻辑单元可以被编程为用作多个预定逻辑功能之一。

4. 发明申请

US20120268163A1 CONFIGURABLE LOGIC CELLS 有权
标题翻译：可配置逻辑电池
公开(公告)号：US20120268163A1
公开(公告)日：2012-10-25
申请号：US13449993
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： H03K19/173
CPC分类号： G06F15/7871 , H03K19/177 , H03K19/17708
摘要： A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.
摘要翻译：处理器包括一个RISC CPU内核; 以及包括一个或多个可配置逻辑单元外围设备的多个外围设备。可配置逻辑单元外设可以被配置为允许实时软件访问处理器的内部配置和信号路径。可配置逻辑单元外设可能具有实时配置控制。

5. 发明申请

US20120268193A1 SELECTING FOUR SIGNALS FROM SIXTEEN INPUTS 有权
标题翻译：从第六代输入选择四个信号
公开(公告)号：US20120268193A1
公开(公告)日：2012-10-25
申请号：US13449687
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , zeke Lundstrum , Fanie Duvenhage
IPC分类号： H03K17/00
CPC分类号： H03K19/1737 , H03K19/17744
摘要： An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.
摘要翻译：一种用于从设备中的多个y信号中选择多个输入信号的装置具有具有多个n至1个多路复用器的交换矩阵，其中每个n至1多路复用器被分配给y信号的n个的不同输入集合其中n至1个多路复用器中的每一个的每组输入信号的小于n个输入信号的子集也是另一n到1个多路复用器的输入信号的子集。

6. 发明申请

US20120268162A1 CONFIGURABLE LOGIC CELLS 审中-公开
标题翻译：可配置逻辑电池
公开(公告)号：US20120268162A1
公开(公告)日：2012-10-25
申请号：US13449850
申请日：2012-04-18
申请人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
发明人： Kevin Lee Kilzer , Sean Steedman , Jerrold S. Zdenek , Vivien N. Delport , Zeke Lundstrum , Fanie Duvenhage
IPC分类号： H03K19/173
CPC分类号： H03K19/17708 , G06F15/7867
摘要： An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.
摘要翻译：根据权利要求的实施例的集成电路装置包括中央处理核心; 以及可操作地耦合到RISC CPU核心的多个外围设备。在一些实施例中，多个外围设备包括至少一个可配置逻辑单元外围设备，其具有比集成电路设备上的输入 - 输出连接更多的输入。在一些实施例中，输入包括来自一个或多个集成电路子系统的一个或多个输入。

7. 发明授权

US08539210B2 Context switching with automatic saving of special function registers memory-mapped to all banks 有权
标题翻译：具有自动保存特殊功能寄存器的上下文切换，内存映射到所有存储区
公开(公告)号：US08539210B2
公开(公告)日：2013-09-17
申请号：US12147746
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F9/48
CPC分类号： G06F9/461
摘要： A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
摘要翻译：微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以被存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

8. 发明授权

US07996647B2 Enhanced microprocessor or microcontroller 有权
标题翻译：增强的微处理器或微控制器
公开(公告)号：US07996647B2
公开(公告)日：2011-08-09
申请号：US12178249
申请日：2008-07-23
申请人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
发明人： Jerrold S. Zdenek , Joseph Julicher , Sean Steedman , Vivien Delport
IPC分类号： G06F12/02
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30101 , G06F9/30138 , G06F9/342 , G06F12/06
摘要： A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.
摘要翻译：处理器设备具有具有线性地址空间的数据存储器，数据存储器可通过多个存储体访问。存储体的至少一个子集被组织成使得子集的每个存储体具有至少第一和第二存储区，其中由多个连续存储体的第二存储区形成连续存储块。提供地址调整单元，当使用预定义的地址范围时，将预定义地址范围内的地址转换为访问所述第二存储区域，使得通过该地址，多个第二存储区域形成连续线性存储器块。

9. 发明申请

US20090144481A1 Enhanced Microprocessor or Microcontroller 有权
标题翻译：增强微处理器或微控制器
公开(公告)号：US20090144481A1
公开(公告)日：2009-06-04
申请号：US12147746
申请日：2008-06-27
申请人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
发明人： Joseph Julicher , Zacharias Marthinus Smit , Sean Steedman , Vivien Delport , Jerrold S. Zdenek , Ryan Scott Ellison , Eric Schroeder
IPC分类号： G06F12/06
CPC分类号： G06F9/461
摘要： A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.
摘要翻译：微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以被存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

10. 发明申请

US20100188014A1 MODULATOR MODULE IN AN INTEGRATED CIRCUIT DEVICE 有权
标题翻译：集成电路设备中的调制器模块
公开(公告)号：US20100188014A1
公开(公告)日：2010-07-29
申请号：US12690258
申请日：2010-01-20
申请人： Zeke R. Lundstrum , Keith Curtis , Sean Steedman , Vivien Delport , Jerrold S. Zdenek
发明人： Zeke R. Lundstrum , Keith Curtis , Sean Steedman , Vivien Delport , Jerrold S. Zdenek
IPC分类号： H05B41/36 , H03C1/00 , H03C3/00
CPC分类号： H03C3/00 , H04L27/122 , H05B41/2828
摘要： An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.
摘要翻译：集成电路装置具有调制器模块，该调制器模块提供包括基于调制器信号选择的一个频率键控开关或交替的两个或多个不同频率或相位之间的调制信号。可以从多个频率源中选择一个或多个频率或相位。将一个频率开启或关闭，或者在至少两个不同频率或相位之间切换可以与两个或更多个不同频率或相位中的一个或两个同步，使得“毛刺”或杂散不被引入到调制信号中。集成电路设备还可以包括处理器，存储器，数字逻辑和输入 - 输出。频率源可能在数字设备内部或外部。调制器信号可以包括从数字设备的数字逻辑和/或处理器产生的串行数据。

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