专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08207613B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08207613B2
公开(公告)日：2012-06-26
申请号：US12718374
申请日：2010-03-05
申请人： Yuki Okukawa , Satoru Takase
发明人： Yuki Okukawa , Satoru Takase
IPC分类号： H01L23/48
CPC分类号： H01L27/101 , H01L27/222 , H01L27/24
摘要： A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.
摘要翻译：一种半导体存储器件，包括：一个包括彼此交叉的第一和第二布线的单元阵列层; 形成在所述电池阵列层下方的第一布线层上的第三布线; 形成在所述电池阵列层上方的第二布线层上的第四布线; 以及在堆叠方向上延伸的用于连接第三和第四布线的接触件，其中所述装置还包括在所述第一和第二布线层之间形成的冗余布线层，所述冗余布线层形成有冗余布线，所述冗余布线具有部分沿与第三和第四布线，第三布线和第三布线以及第三布线和第四布线中的至少一个相同的方向延伸，并且第四布线和冗余布线通过沿与沿着相同方向延伸的部分布置的多个触点连接第三或第四布线。

2. 发明授权

US07978499B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07978499B2
公开(公告)日：2011-07-12
申请号：US12556272
申请日：2009-09-09
申请人： Koji Hosono , Satoru Takase
发明人： Koji Hosono , Satoru Takase
IPC分类号： G04B25/02 , G04B27/00
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0011 , G11C13/0069 , G11C2013/0078 , G11C2213/71 , G11C2213/72
摘要： A semiconductor storage device includes: a memory cell array having memory cells; and a control circuit configured to apply a first voltage to a selected one of first wirings as well as a second voltage to a selected one of second wirings. The control circuit includes: a signal output circuit configured to output a first signal based on a first current flowing through a selected memory cell and a reference current; and a current retaining circuit configured to retain a second current flowing through the first wirings or a wiring electrically connected to the first wirings during a certain period of time. The signal output circuit is configured to determine the first current based on the second current retained by the current retaining circuit. The control circuit is configured to stop application of the first voltage to the first wirings based on the first signal.
摘要翻译：半导体存储装置包括：具有存储单元的存储单元阵列; 以及控制电路，被配置为将第一电压施加到所选择的第一布线中的一个，以及将第二电压施加到所选择的第二布线中的一个。控制电路包括：信号输出电路，被配置为基于流过所选择的存储单元的第一电流和参考电流来输出第一信号; 以及电流保持电路，其被配置为在一定时间段期间保持流过所述第一布线的第二电流或电连接到所述第一布线的布线。信号输出电路被配置为基于由电流保持电路保持的第二电流来确定第一电流。控制电路被配置为基于第一信号停止将第一电压施加到第一布线。

3. 发明授权

US07800935B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07800935B2
公开(公告)日：2010-09-21
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 ＆Dgr; R2的关系。

4. 发明申请

US20090175077A1 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20090175077A1
公开(公告)日：2009-07-09
申请号：US12324953
申请日：2008-11-28
申请人： Satoru TAKASE , Shigeo OHSHIMA
发明人： Satoru TAKASE , Shigeo OHSHIMA
IPC分类号： G11C16/02 , G11C8/00 , G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C7/06 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/3418
摘要： This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.
摘要翻译：本公开涉及一种存储器，包括：延伸到第一方向的字线; 位线延伸到与第一方向交叉的第二方向; 包括单元块的存储单元阵列，每个单元块包括分别对应于字线和位线的交点提供的存储单元; 以及对应于所述位线的感测放大器，其中所述感测放大器将存储在所述存储单元阵列内的第一单元块中的现有数据复制到多个存储器单元，所述存储单元包括在与所述第一和第三单元块不同的第二和第三单元块中并且在字线的延伸方向上交替布置，并且还在位线的延伸方向上交替布置，并且读出放大器在输出数据时从第二单元块或第三单元块读取数据到感应放大器外面。

5. 发明申请

US20090135637A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20090135637A1
公开(公告)日：2009-05-28
申请号：US12245152
申请日：2008-10-03
申请人： Satoru TAKASE
发明人： Satoru TAKASE
IPC分类号： G11C5/02 , G11C11/00 , G11C8/08
CPC分类号： G11C13/0007 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2213/32 , G11C2213/71 , G11C2213/72 , H01L27/101
摘要： A resistance change memory device including: a cell array having a resistance change type of memory cells disposed at the cross-points of word lines and bit lines, the resistance value of the memory cell being reversibly settable; a word line driver circuit configured to apply a selecting drive voltage to one selected in the word lines; and a bit line driver circuit configured to drive multiple bit lines in such a manner that a set mode and a reset mode are set simultaneously for multiple memory cells selected by the selected word line, the set mode being for changing a selected memory cell from a first resistance state into a second resistance state while the reset mode is for changing a selected memory cell from the second resistance state into the first resistance state.
摘要翻译：一种电阻变化存储装置，包括：具有设置在字线和位线的交叉点的存储单元的电阻变化型的单元阵列，可逆地设定存储单元的电阻值; 字线驱动器电路，被配置为向所述字线中选择的一个施加选择驱动电压; 以及位线驱动电路，其被配置为以这样的方式驱动多个位线，使得对于由所选择的字线选择的多个存储器单元同时设置设置模式和复位模式，所述设置模式用于将选择的存储器单元从第一电阻状态变为第二电阻状态，而复位模式用于将所选择的存储单元从第二电阻状态改变为第一电阻状态。

6. 发明申请

US20080112236A1 Systems and Methods for Improving Memory Reliability by Selectively Enabling Word Line Signals 有权
标题翻译：通过选择性地启用字线信号来提高存储器可靠性的系统和方法
公开(公告)号：US20080112236A1
公开(公告)日：2008-05-15
申请号：US11558045
申请日：2006-11-09
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C8/08 , G11C11/417
摘要： Systems and methods for reducing instability and writability problems arising from relative variations between a memory cell voltage (Vcell) and a logic voltage (Vdd) by inhibiting assertion of word line signals that enable accesses to the memory cells when the voltages are not within an acceptable operating range. One embodiment comprises a system having a critical condition detector configured to monitor the voltages and to determine whether the voltages are within an acceptable range. When the voltages are not within the acceptable range, the system inhibits assertion of the word lines to the memory cells. Memory accesses which fail because of the inhibited word line signals are retried by a memory controller when the critical conditions that caused the signals to be inhibited no longer exist.
摘要翻译：用于通过禁止当电压不在可接受的范围内访问存储器单元的字线信号的断言来减少存储器单元电压（Vcell）和逻辑电压（Vdd）之间相对变化引起的不稳定性和可编写性问题的系统和方法工作范围。一个实施例包括具有临界状态检测器的系统，其被配置为监视电压并确定电压是否在可接受的范围内。当电压不在可接受范围内时，系统禁止对存储单元的字线断言。当导致信号被禁止的关键条件不再存在时，由存储器控制器重试由于禁止字线信号而失败的存储器访问。

7. 发明申请

US20080062747A1 Systems and methods for improving memory reliability 失效
标题翻译：提高内存可靠性的系统和方法
公开(公告)号：US20080062747A1
公开(公告)日：2008-03-13
申请号：US11530271
申请日：2006-09-08
申请人： Satoru Takase , Takehito Sasaki
发明人： Satoru Takase , Takehito Sasaki
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C5/143 , G11C5/147
摘要： Systems and methods for reducing instability and writability problems arising from relative variations between voltages at which memory cells and logic components that access the memory cells operate by inhibiting memory accesses when the voltages are not within an acceptable operating range. One embodiment comprises a pipelined processor having logic components which receive power at a first voltage and a set of SRAM cells which receive power at a second voltage. A critical condition detector is configured to monitor the first and second voltages and to determine whether the ratio of these voltages is within an acceptable range. When the voltages are not within the acceptable range, an exception is generated, and an exception handler stalls the processor pipeline to inhibit accesses to the SRAM cells. When the voltages return to the acceptable range, the exception handler resumes the pipeline and completes handling of the exception.
摘要翻译：用于减少由电压之间的相对变化引起的不稳定性和可编写性问题的系统和方法，其中存储单元和访问存储器单元的逻辑组件通过在电压不在可接受的工作范围内时禁止存储器访问而工作。一个实施例包括流水线处理器，其具有在第一电压处接收功率的逻辑部件和以第二电压接收功率的一组SRAM单元。临界条件检测器被配置为监视第一和第二电压并且确定这些电压的比率是否在可接受的范围内。当电压不在可接受范围内时，产生异常，异常处理程序使处理器流水线停止以禁止对SRAM单元的访问。当电压返回到可接受的范围时，异常处理程序将恢复流水线并完成异常的处理。

8. 发明申请

US20070297256A1 Systems and Methods for Data Transfers Between Memory Cells 有权
标题翻译：记忆单元之间数据传输的系统和方法
公开(公告)号：US20070297256A1
公开(公告)日：2007-12-27
申请号：US11425438
申请日：2006-06-21
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： G11C7/02
CPC分类号： G11C7/1048 , G11C5/063 , G11C7/065 , G11C11/4091 , G11C11/4093
摘要： Systems and methods for reducing the latency of data transfers between memory cells by enabling data to be transferred directly between sense amplifiers in the memory system. In one embodiment, a memory system uses a conventional DRAM memory structure having a pair of first-level sense amplifiers, a second-level sense amplifier and control logic for the sense amplifiers. Each of the sense amplifiers is configured to be selectively coupled to a data line. In a direct data transfer mode, the control logic generates control signals that cause the sense amplifiers to transfer data from a first one of the first-level sense amplifiers (a source sense amplifier) to the second-level sense amplifier, and from there to a second one of the first-level sense amplifiers (a destination sense amplifier.) The structure of these sense amplifiers is conventional, and the operation of the system is enabled by modified control logic.
摘要翻译：通过使数据能够在存储器系统中的读出放大器之间直接传输来减少存储器单元之间的数据传输的延迟的系统和方法。在一个实施例中，存储器系统使用具有一对第一电平读出放大器，第二电平读出放大器和用于读出放大器的控制逻辑的常规DRAM存储器结构。每个读出放大器被配置为选择性地耦合到数据线。在直接数据传输模式中，控制逻辑产生控制信号，使得读出放大器将数据从第一级读出放大器（源读出放大器）的第一级传输到第二级读出放大器，第一级读出放大器（目标读出放大器）中的第二级。这些读出放大器的结构是常规的，并且系统的操作由修改的控制逻辑实现。

9. 发明申请

US20060267691A1 System and method for phase-locked loop leak compensation 失效
标题翻译：锁相环泄漏补偿系统及方法
公开(公告)号：US20060267691A1
公开(公告)日：2006-11-30
申请号：US11136817
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/00
CPC分类号： H03L7/0891 , H03L7/18
摘要： Phased-lock loop (PLL) system and method for compensating current leakage where current leakage may include gate-leak current attributable to a gate capacitor. In particular, providing a compensation current to an input node of a voltage-controlled oscillator (VCO) to substantially compensate current leakage and therefore reduce PLL jitter. The PLL circuit includes a compensation charge pump which receives input from a counter and in turn provides a counter-value-proportional compensation current. The counter value increments and decrements according to up and down inputs from a phase frequency detector. The counter value is fixed when the PLL circuit is locked. The PLL circuit is driven to lock by the compensation charge pump, with or without the aid of another charge pump. While the PLL is locked, the compensation charge pump may provide a fixed counter-value-proportional compensation current.
摘要翻译：用于补偿电流泄漏的相位锁定环路（PLL）系统和方法，其中电流泄漏可能包括归属于栅极电容器的栅极漏电流。特别地，向压控振荡器（VCO）的输入节点提供补偿电流，以基本上补偿电流泄漏并因此降低PLL抖动。 PLL电路包括补偿电荷泵，其接收来自计数器的输入，并且进而提供反值比例补偿电流。计数器值根据相位频率检测器的上下输入递增和递减。 PLL电路锁定时，计数器值固定。驱动PLL电路由补偿电荷泵锁定，无论是否使用另一个电荷泵。当PLL被锁定时，补偿电荷泵可以提供固定的反值比例补偿电流。

10. 发明申请

US20060267642A1 System and method for lock detection of a phase-locked loop circuit 失效
标题翻译：锁相环电路锁定检测系统及方法
公开(公告)号：US20060267642A1
公开(公告)日：2006-11-30
申请号：US11137072
申请日：2005-05-25
申请人： Satoru Takase
发明人： Satoru Takase
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/089 , H03L7/0895 , H03L2207/14 , Y10S331/02
摘要： Systems and methods for detecting phase-locked loop circuit lock. In particular, a lock detector configured to detect PLL stability for a user-defined period of time prior to asserting a PLL-lock-detected output. Stability may be indicated by a counter inserted into a PLL circuit and arranged between a phase-frequency detector and a charge pump. Because the counter value is acted upon by the phase-frequency detector, PLL lock is indicated by counter value stability. The digital counter value may be provided to a digital charge pump and a lock detector simultaneously. The lock detector includes registers and difference detectors to determine when the difference between counter values is below a user-defined tolerance. The lock detector may include a variable timer to avoid false indications of lock which may occur when counter values are sampled with the same frequency as a fluctuation frequency of the counter value.
摘要翻译：用于检测锁相环电路锁的系统和方法。特别地，锁定检测器被配置为在断言PLL锁定检测到的输出之前检测用户定义的时间段的PLL稳定性。稳定性可以由插入PLL电路中的计数器指示并且布置在相位频率检测器和电荷泵之间。由于计数器值由相位频率检测器作用，PLL锁定由计数器值稳定性指示。数字计数器值可以同时提供给数字电荷泵和锁定检测器。锁定检测器包括寄存器和差分检测器，用于确定计数器值之间的差异何时低于用户定义的公差。锁定检测器可以包括可变定时器，以避免在以与计数器值的波动频率相同的频率对计数器值进行采样时可能发生的锁定的错误指示。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式