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1. 发明授权

US09973196B2 Clock synchronizer 有权
公开(公告)号：US09973196B2
公开(公告)日：2018-05-15
申请号：US15085821
申请日：2016-03-30
申请人： NXP B.V.
发明人： Jos Verlinden , Remco van de Beek , Stefan Mendel
IPC分类号： H03L7/087 , H03L7/197 , H03L7/23 , H03L7/107 , H03L7/18 , H04B5/00 , H04L7/033 , H04W4/00
CPC分类号： H03L7/087 , H03L7/1075 , H03L7/1803 , H03L7/197 , H03L7/1974 , H03L7/235 , H04B5/0031 , H04L7/0331 , H04W4/80
摘要： Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

2. 发明申请

US20130147529A1 NEAR-INTEGER CHANNEL SPUR MITIGATION IN A PHASE-LOCKED LOOP 有权
标题翻译：相位锁定环路中的近整数信道减速
公开(公告)号：US20130147529A1
公开(公告)日：2013-06-13
申请号：US13323195
申请日：2011-12-12
申请人： Raghu Ganesan , Saket Jalan
发明人： Raghu Ganesan , Saket Jalan
IPC分类号： H03L7/06
CPC分类号： H03L7/1803
摘要： A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop.
摘要翻译：一种方法包括将锁相环的输入频率的分频的频率成分的干扰重新定位到锁相环的截止频率之外的频率上，当基准时钟频率输入和输出频率之间存在接近整数关系时，具有通过其反馈路径输入的基准时钟频率的锁相环。该方法还包括通过锁相环来过滤杂散频率分量。

3. 发明申请

US20050030114A1 Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system 有权
标题翻译：在可编程锁相环（PLL）系统中模拟实现扩频调频
公开(公告)号：US20050030114A1
公开(公告)日：2005-02-10
申请号：US10888549
申请日：2004-07-09
申请人： Gregory Starr , Wanli Chang
发明人： Gregory Starr , Wanli Chang
IPC分类号： H03L7/089 , H03L7/093 , H03L7/18 , H03M1/80 , H04B1/707 , H04L7/033 , H03B29/00
CPC分类号： H03L7/0896 , H03L7/0898 , H03L7/093 , H03L7/18 , H03L7/1803 , H03M1/808 , H04B1/707
摘要： A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.
摘要翻译：描述PLL电路。 PLL电路包括：信号发生器; 以及耦合到信号发生器的扩频调制器，其中扩频调制器接收控制电压作为输入，并且响应于控制电压向信号发生器提供扩频控制电压。在一个实施例中，扩频调制器包括至少一个选择器，其中至少一个选择器选择对应于扩展模式的多个电压电平和扩展频谱调制器的扩展百分比。

4. 发明申请

US20160294398A1 CLOCK SYNCHRONIZER 有权
标题翻译：时钟同步器
公开(公告)号：US20160294398A1
公开(公告)日：2016-10-06
申请号：US15085821
申请日：2016-03-30
申请人： NXP B.V.
发明人： Jos Verlinden , Remco van de Beek , Stefan Mendel
IPC分类号： H03L7/087 , H03L7/18 , H04W4/00 , H04L7/033 , H04B5/00 , H03L7/107 , H03L7/197
CPC分类号： H03L7/087 , H03L7/1075 , H03L7/1803 , H03L7/197 , H03L7/1974 , H03L7/235 , H04B5/0031 , H04L7/0331 , H04W4/80
摘要： Apparatus for clock synchronisation comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.
摘要翻译：用于时钟同步的装置包括第一锁相环（405）和第二锁相环（400）。第一锁相环（405）被配置为接收具有参考频率的参考信号（Fcrystal），并且可操作以产生具有作为参考频率倍数的输出频率的输出信号（Fout）。第一锁相环（405）包括响应于控制信号来控制多个的分频器（428）。第二锁相环（400）被配置为确定输出信号（Fout）和输入信号（Fantenna）之间的相位误差，并将控制信号提供给第一锁相环（405）。第二锁相环（400）包括相位调整装置（450），可操作以通过在一段持续时间内改变控制信号来调节输入和输出信号之间的相位差。

5. 发明授权

US08971455B2 Near-integer channel spur mitigation in a phase-locked loop 有权
标题翻译：锁相环中的近整数通道刺激减轻
公开(公告)号：US08971455B2
公开(公告)日：2015-03-03
申请号：US13323195
申请日：2011-12-12
申请人： Raghu Ganesan , Saket Jalan
发明人： Raghu Ganesan , Saket Jalan
IPC分类号： H03L7/06
CPC分类号： H03L7/1803
摘要： A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop.
摘要翻译：一种方法包括将锁相环的输入频率的分频的频率成分的干扰重新定位到锁相环的截止频率之外的频率上，当基准时钟频率输入和输出频率之间存在接近整数关系时，具有通过其反馈路径输入的基准时钟频率的锁相环。该方法还包括通过锁相环来过滤杂散频率分量。

6. 发明授权

US08558575B1 Clock generation for N.5 modulus divider 有权
标题翻译： N.5模数分频器的时钟生成
公开(公告)号：US08558575B1
公开(公告)日：2013-10-15
申请号：US13427955
申请日：2012-03-23
申请人： Brian Abernethy
发明人： Brian Abernethy
IPC分类号： H03K19/21
CPC分类号： H03K21/10 , H03K19/21 , H03K23/68 , H03L7/1803 , H03L7/1972 , H03L7/1974
摘要： A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.
摘要翻译：提供一种用于产生用于N.5模数分频的输出时钟的系统。边缘滑移电路接受模数计数，除数选择信号和具有大于模数计数频率的频率的时钟信号。边缘滑移电路还具有接收输出时钟信号的输入端和用于提供时钟滑差信号（NE）的输出。异或（XOR）具有接受缓冲时钟信号（NF）和时钟转移信号（NE）的输入。 XOR具有输出以提供输出时钟信号。当时钟滑移信号不改变逻辑电平时，输出时钟信号的频率等于缓冲的时钟信号频率，没有跳过的时钟沿。或者，当时钟滑移信号改变逻辑电平时，输出时钟信号频率等于具有跳过时钟边沿的缓冲时钟信号频率。

7. 发明申请

US20170346494A1 METHOD OF SPEEDING UP OUTPUT ALIGNMENT IN A DIGITAL PHASE LOCKED LOOP 审中-公开
公开(公告)号：US20170346494A1
公开(公告)日：2017-11-30
申请号：US15597726
申请日：2017-05-17
申请人： Microsemi Semiconductor ULC
发明人： Changhui Cathy Zhang , Qu Gary Jin , Mark A. Warriner , Kamran Rahbar
IPC分类号： H03L7/10 , H03K5/135 , H03L7/091 , H03L7/18 , H03L7/099 , H03K5/00
CPC分类号： H03L7/103 , H03K5/135 , H03K2005/00104 , H03L7/085 , H03L7/091 , H03L7/0991 , H03L7/10 , H03L7/1803 , H03L2207/50
摘要： To speed up output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure the output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, a group of the output pulses is advanced during the alignment procedure to reduce the spacing between them. After determining the delay value averaged over the group of output pulses subsequent output pulses are restored to their normal spacing and time locations.

8. 发明授权

US07310009B2 Phase locked loop circuit having deadlock protection circuit and methods of operating same 失效
标题翻译：具有死锁保护电路的锁相环电路及其操作方法
公开(公告)号：US07310009B2
公开(公告)日：2007-12-18
申请号：US11291415
申请日：2005-12-01
申请人： Jung-hoon Oh
发明人： Jung-hoon Oh
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L7/18 , H03L7/1803
摘要： A phase locked loop (PLL) circuit having a deadlock protection circuit and a deadlock protection method of the PLL circuit are provided. The PLL circuit includes: a phase frequency detector, which receives an input clock signal and a divided clock signal and compares the phase and frequency of the input clock signal with the phase and frequency of the divided clock signal; a charge pump, which receives an output signal of the phase frequency detector; a voltage-controlled oscillator, which oscillates in response to an output voltage of the charge pump; a main divider, which divides the frequency of an first output clock signal of the voltage-controlled oscillator and outputs the divided clock signal as the division result; and a deadlock protection circuit, which is electrically coupled to an output port of the voltage-controlled oscillator and an input port of the main divider, and divides the frequency of the first output clock signal of the voltage-controlled oscillator and then provides the division result to the main divider if the frequency of the first output clock signal of the voltage-controlled oscillator is above a threshold frequency.
摘要翻译：提供了具有PLL电路的死锁保护电路和死锁保护方法的锁相环（PLL）电路。 PLL电路包括：相位频率检测器，其接收输入时钟信号和分频时钟信号，并将输入时钟信号的相位和频率与分频时钟信号的相位和频率进行比较; 电荷泵，其接收相位频率检测器的输出信号; 电压控制振荡器，其响应于电荷泵的输出电压而振荡; 主分压器，其分压电压控制振荡器的第一输出时钟信号的频率，并输出分频时钟信号作为除法结果; 以及死电源保护电路，其电耦合到压控振荡器的输出端口和主分压器的输入端口，并且分压压控振荡器的第一输出时钟信号的频率，然后提供除法如果压控振荡器的第一输出时钟信号的频率高于阈值频率，则导致主分压器。

9. 发明申请

US20030160641A1 Analog implementation of spread spectrum frequency modulation in a programmable phase locked loop (PLL) system 有权
标题翻译：在可编程锁相环（PLL）系统中模拟实现扩频调频
公开(公告)号：US20030160641A1
公开(公告)日：2003-08-28
申请号：US10138461
申请日：2002-05-03
发明人： Gregory W. Starr , Wanli Chang
IPC分类号： H03B029/00
CPC分类号： H03L7/0896 , H03L7/0898 , H03L7/093 , H03L7/18 , H03L7/1803 , H03M1/808 , H04B1/707
摘要： A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.
摘要翻译：描述PLL电路。 PLL电路包括：信号发生器; 以及耦合到信号发生器的扩频调制器，其中扩频调制器接收控制电压作为输入，并且响应于控制电压向信号发生器提供扩频控制电压。在一个实施例中，扩频调制器包括至少一个选择器，其中至少一个选择器选择对应于扩展模式的多个电压电平和扩展频谱调制器的扩展百分比。

10. 发明授权

US09998129B1 PLL post divider phase continuity 有权
公开(公告)号：US09998129B1
公开(公告)日：2018-06-12
申请号：US15711962
申请日：2017-09-21
申请人： QUALCOMM Incorporated
发明人： Jingcheng Zhuang , Jianyun Hu , Animesh Paul , Xinhua Chen , Frederic Bossu
IPC分类号： H03D3/24 , H03L7/18 , H03L7/099 , H04L7/00 , H03L7/197 , H04L7/033 , H03L7/093
CPC分类号： H03L7/1803 , H03C3/0975 , H03L7/093 , H03L7/099 , H03L7/0992 , H03L7/18 , H03L7/197 , H03L7/1976 , H04L7/00 , H04L7/0008 , H04L7/033
摘要： A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

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