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1. 发明申请

US20180342972A1 MOTOR CONTROL SYSTEM AND METHOD FOR DETECTING ABNORMALITY IN RESOLVER/DIGITAL CONVERTER 审中-公开
公开(公告)号：US20180342972A1
公开(公告)日：2018-11-29
申请号：US15939599
申请日：2018-03-29
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： Kazuya YAMAMOTO , Yu SASAKI
IPC分类号： H02P27/04 , H03M1/10
CPC分类号： H02P27/045 , H02P29/0241 , H03M1/1076 , H03M1/645
摘要： A motor control system includes a motor, a resolver configured to detect a rotation angle of the motor, a resolver/digital converter configured to convert an analog angle signal output from the resolver into a digital angle signal, and a motor control unit configured to control the motor based on the digital angle signal output from the resolver/digital converter and determine, when an integrated value obtained by integrating the digital angle signal at a predetermined time interval is not within a threshold range, that the resolver/digital converter is abnormal. The motor control unit increases the time interval for the integration when a rotation speed of the motor decreases and decreases the time interval for the integration when the rotation speed of the motor increases.

2. 发明申请

US20180287625A1 Failure Determination Circuit, Physical Quantity Measurement Device, Electronic Apparatus, Vehicle, And Failure Determination Method 审中-公开
公开(公告)号：US20180287625A1
公开(公告)日：2018-10-04
申请号：US15927424
申请日：2018-03-21
申请人： Seiko Epson Corporation
发明人： Noriyuki MURASHIMA
IPC分类号： H03M1/10 , H03M1/12 , H03M3/02 , G01R31/28 , G01R31/316
CPC分类号： H03M1/1076 , G01R31/2884 , G01R31/316 , H03M1/12 , H03M3/02
摘要： A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.

3. 发明授权

US09787317B2 Systems and methods for analog to digital converter failure identification 有权
公开(公告)号：US09787317B2
公开(公告)日：2017-10-10
申请号：US15417083
申请日：2017-01-26
申请人： Schweitzer Engineering Laboratories, Inc.
发明人： Travis C. Mallett
IPC分类号： H03M1/06 , H03M1/10 , H03F3/04
CPC分类号： H03M1/1071 , G01R19/2509 , G01R22/10 , G01R35/00 , H03F3/04 , H03F2200/129 , H03M1/0631 , H03M1/1009 , H03M1/1076 , H03M1/1245 , H03M1/34
摘要： Systems and methods for identifying and reporting failures of an analog to digital (A/D) conversion system are presented. The systems and methods may detect and report a problem of input circuitry of an A/D converter and/or an A/D converter itself. For example, an identifiable characteristic can be introduced into the input signal provided to an A/D converter. The A/D converter may output a digital value that includes the identifiable characteristic of the A/D converter input. A monitoring system may determine and/or report a change in, or a failure of, the A/D converter or input circuitry thereto, based on the identification, non-existence of, or variation in the identifiable characteristic in the digital output.

4. 发明授权

US09698809B1 Systems and methods for analog to digital converter failure identification 有权
公开(公告)号：US09698809B1
公开(公告)日：2017-07-04
申请号：US15213993
申请日：2016-07-19
申请人： Schweitzer Engineering Laboratories, Inc.
发明人： Travis C Mallett
IPC分类号： H03M1/10 , H03M1/12 , H03M3/00
CPC分类号： H03M1/1071 , H03M1/1076 , H03M1/1085 , H03M1/12 , H03M1/1245 , H03M3/458
摘要： Disclosed are systems and methods for identifying and reporting failures of an analog to digital (A/D) conversion system. An A/D conversion system includes a test signal generator configured to generate a test signal including an identifiable characteristic, an A/D converter configured to convert an analog signal measured at an input of the A/D converter to a digital output, and signal injection circuitry configured to inject at least a portion of the test signal from the test signal generator as an injected signal into the analog signal using trace-to-trace crosstalk. A method includes determining whether the digital output generated by the A/D converter indicates the identifiable characteristic.

5. 发明授权

US09157948B2 Semiconductor device and fault diagnosis system 有权
标题翻译：半导体器件和故障诊断系统
公开(公告)号：US09157948B2
公开(公告)日：2015-10-13
申请号：US13912474
申请日：2013-06-07
申请人： Renesas Electronics Corporation
发明人： Kazutoshi Tsuda
IPC分类号： G01R31/02 , G01R31/26 , H03M1/10 , H03M3/00 , H03M1/12
CPC分类号： G01R31/26 , H03M1/1076 , H03M1/12 , H03M3/378 , H03M3/458
摘要： Provided is a semiconductor device capable of performing fault detection on a circuit executing an AD conversion operation during the AD conversion operation. The semiconductor device includes an analog to digital conversion unit that converts a second analog signal into a first digital signal, in which the second analog signal is obtained by adding a first analog signal and an offset signal with a signal band different from the first analog signal, a signal extraction unit that extracts from the first digital signal a second digital signal corresponding to the signal band of the offset signal, and a fault detection unit that detects a fault in the analog to digital conversion unit based on the second digital signal and a setting value that is set upon generating the offset signal.
摘要翻译：提供了能够在AD转换操作期间对执行AD转换操作的电路进行故障检测的半导体器件。半导体器件包括模数转换单元，其将第二模拟信号转换为第一数字信号，其中通过将第一模拟信号和偏移信号与不同于第一模拟信号的信号频带相加来获得第二模拟信号信号提取单元，从第一数字信号提取与偏移信号的信号频带相对应的第二数字信号;以及故障检测单元，其基于第二数字信号和模拟数字转换单元检测模数转换单元中的故障，产生偏移信号时设定的设定值。

6. 发明授权

US08994569B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08994569B2
公开(公告)日：2015-03-31
申请号：US14023642
申请日：2013-09-11
申请人： Renesas Electronics Corporation
发明人： Tomohiko Ebata , Takuji Aso
IPC分类号： H03M1/12 , H03M1/10
CPC分类号： H03M1/1076 , H03M1/12 , H03M1/1225
摘要： The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.
摘要翻译：半导体集成电路器件包括在模拟/数字转换电路的输入端口A [k]和输入端子Ain之间的T型开关电路TS [k]，并且包括第一，第二和第三PMOS晶体管MP1 ，MP2和MPc以及第一，第二和第三NMOS晶体管MN1，MN2和MNc; 以及用于将输入端子Ain预充电到电源电压VCCA的第四PMOS晶体管MPu。在检测到从输入端口A [k]到信号输入端子Vint [k]的断开的存在或不存在时，首先，输入端子Ain经由第四PMOS晶体管MPu预充电到电源电压VCCA，第二NMOS晶体管MN2和第二PMOS晶体管MP2也被导通，并且第一NMOS晶体管MN1，第一PMOS晶体管MP1，第三PMOS晶体管MPc和第三NMOS晶体管MNc截止。

7. 发明授权

US08779961B2 Scalable successive-approximation-register analog-to-digital converter 有权
标题翻译：可扩展的逐次逼近寄存器模数转换器
公开(公告)号：US08779961B2
公开(公告)日：2014-07-15
申请号：US13666251
申请日：2012-11-01
申请人： Marvell International Ltd.
发明人： Sehat Sutardja , Giovanni Antonio Cesura , Francesco Rezzi , Rinaldo Castello
IPC分类号： H03M1/20 , H03M1/12 , H03M1/00
CPC分类号： H03M1/20 , A01K79/00 , A23K50/80 , H03M1/002 , H03M1/0643 , H03M1/0678 , H03M1/1076 , H03M1/121 , H03M1/468
摘要： A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.
摘要翻译：一种包括被配置为产生时钟的时钟发生器的系统; 多个模数转换器，每个被配置为基于时钟转换信号，并且响应于基于时钟转换信号来输出第一位数; 以及平均模块，被配置为从所述多个模数转换器中的每一个接收所述第一数量的位，并输出第二数量的位。第二位数大于第一位数。

8. 发明申请

US20140085121A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20140085121A1
公开(公告)日：2014-03-27
申请号：US14023642
申请日：2013-09-11
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Tomohiko EBATA , Takuji ASO
IPC分类号： H03M1/12
CPC分类号： H03M1/1076 , H03M1/12 , H03M1/1225
摘要： The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.
摘要翻译：半导体集成电路器件包括在模拟/数字转换电路的输入端口A [k]和输入端子Ain之间的T型开关电路TS [k]，并且包括第一，第二和第三PMOS晶体管MP1 ，MP2和MPc以及第一，第二和第三NMOS晶体管MN1，MN2和MNc; 以及用于将输入端子Ain预充电到电源电压VCCA的第四PMOS晶体管MPu。在检测到从输入端口A [k]到信号输入端子Vint [k]的断开的存在或不存在时，首先，输入端子Ain经由第四PMOS晶体管MPu预充电到电源电压VCCA，第二NMOS晶体管MN2和第二PMOS晶体管MP2也被导通，并且第一NMOS晶体管MN1，第一PMOS晶体管MP1，第三PMOS晶体管MPc和第三NMOS晶体管MNc截止。

9. 发明授权

US08629792B2 A/D conversion circuit and test method 有权
标题翻译： A / D转换电路和测试方法
公开(公告)号：US08629792B2
公开(公告)日：2014-01-14
申请号：US13137621
申请日：2011-08-30
申请人： Tomoya Katsuki , Shinichirou Saitou
发明人： Tomoya Katsuki , Shinichirou Saitou
IPC分类号： H03M1/00
CPC分类号： H03M1/1076 , H03M1/1225
摘要： An electric device includes first, second and third selectors. A first node connects to a first input of the first selector, a second node connects to a first input of the second selector, a third node connects to a second input of the first selector, and a fourth node connects to a second input of the second selector. A first switch connects to the first node, and a second switch connects to the second node. A first capacitor connects between the first switch and the third node, and a second capacitor connects between the second switch and the fourth node. A fifth node connects between an output of the first selector and a first input of the third selector, and a sixth node connects between an output of the second selector and a second input of the third selector. An A/D converter connects to an output of the third selector.
摘要翻译：电气设备包括第一，第二和第三选择器。第一节点连接到第一选择器的第一输入端，第二节点连接到第二选择器的第一输入端，第三节点连接到第一选择器的第二输入端，第四节点连接到第二选择器的第二输入端第二选择器。第一交换机连接到第一节点，第二交换机连接到第二节点。第一电容器连接在第一开关和第三节点之间，第二电容器连接在第二开关和第四节点之间。第五节点连接在第一选择器的输出端和第三选择器的第一输入端之间，第六节点连接在第二选择器的输出端和第三选择器的第二输入端之间。 A / D转换器连接到第三选择器的输出。

10. 发明授权

US08610613B2 Semiconductor integrated circuit device 有权
公开(公告)号：US08610613B2
公开(公告)日：2013-12-17
申请号：US13397733
申请日：2012-02-16
申请人： Tomohiko Ebata , Takuji Aso
发明人： Tomohiko Ebata , Takuji Aso
IPC分类号： H03M1/12
CPC分类号： H03M1/1076 , H03M1/12 , H03M1/1225
摘要： The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

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