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1. 发明申请

US20180219559A1 DELTA MODULATOR WITH VARIABLE FEEDBACK GAIN, ANALOG-TO-DIGITAL CONVERTER INCLUDING THE DELTA MODULATOR, AND COMMUNICATION DEVICE INCLUDING THE DELTA MODULATOR 审中-公开
公开(公告)号：US20180219559A1
公开(公告)日：2018-08-02
申请号：US15702962
申请日：2017-09-13
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Jae-hoon LEE , Jong-woo LEE , Chilun LO , Seung-hyun OH , Jong-mi LEE
IPC分类号： H03M3/00
CPC分类号： H03M3/464 , H03M3/426 , H03M3/434 , H03M3/436 , H03M3/498
摘要： A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

2. 发明申请

US20170288439A1 SIGNAL PROCESSING CIRCUIT, COULOMB COUNTER CIRCUIT, AND ELECTRONIC DEVICE 审中-公开
公开(公告)号：US20170288439A1
公开(公告)日：2017-10-05
申请号：US15474250
申请日：2017-03-30
申请人： ROHM CO., LTD.
发明人： Yoichi TAMEGAI
IPC分类号： H02J7/00 , G01R31/36 , H03M3/00
CPC分类号： H02J7/0078 , G01R31/3833 , H02J7/0047 , H02J7/0052 , H02J7/0083 , H02J7/0091 , H02J2007/005 , H02J2007/0059 , H03M3/378 , H03M3/468 , H03M3/472 , H03M3/498
摘要： A signal processing circuit includes: a plurality of A/D conversion units of a plurality of channels, each of plurality of the A/D conversion units including an amplifier configured to amplify an input analog signal and an A/D converter configured to convert an output signal from the amplifier into a digital signal, wherein at least one of operation parameters of the amplifier and the A/D converter is set individually for each of the plurality of channels.

3. 发明申请

US20160182073A1 EFFICIENT CALIBRATION OF ERRORS IN MULTI-STAGE ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：多级模拟数字转换器中的错误的有效校准
公开(公告)号：US20160182073A1
公开(公告)日：2016-06-23
申请号：US14955916
申请日：2015-12-01
申请人： ANALOG DEVICES, INC.
发明人： CARROLL C. SPEIR , ERIC OTTE , JEFFREY PAUL BRAY
IPC分类号： H03M1/10 , H03M1/46 , H03M3/00 , H03M1/12
CPC分类号： H03M1/128 , H03M1/1019 , H03M1/1028 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/46 , H03M1/462 , H03M1/468 , H03M3/382 , H03M3/498
摘要： Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.
摘要翻译：模数转换器（ADC）可能会产生可能影响其性能的错误。为了提高性能，已经使用许多技术来补偿或纠正错误。当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。片上微处理器对于随机时间交织ADC特别有用。此外，随机采样ADC可以并行添加到主ADC用于校准目的。此外，整个系统可以包括用于校正ADC中的错误的有效实现。

4. 发明申请

US20140361913A1 COMMUNICATION SYSTEM AND SAMPLE RATE CONVERTER THEREOF 有权
标题翻译：通信系统和采样率转换器
公开(公告)号：US20140361913A1
公开(公告)日：2014-12-11
申请号：US14283301
申请日：2014-05-21
申请人： MStar Semiconductor, Inc.
发明人： Ming-Yu Hsieh , Shih-Chieh Yen , Khurram Muhammad
IPC分类号： H03M1/66 , H03M3/00
CPC分类号： H03M1/66 , H03H17/0294 , H03H17/0621 , H03M3/30 , H03M3/496 , H03M3/498
摘要： A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.
摘要翻译：提供了包括可配置采样率转换器和控制器的通信系统。可配置采样率转换器，被配置为将具有第一采样率的数字信号转换为具有第二采样率的转换信号，其可在第一配置和第二配置中的一个中操作。控制器被配置为根据至少一个条件动态地控制采样率转换器以工作在第一配置和第二配置之一中。

5. 发明授权

US07880655B2 System, in particular for digitizing a time-continuous and value-continuous periodic signal with a firmly predefined number of samples per period 有权
标题翻译：系统，特别是用于以每个周期的牢固预定数量的采样数字化时间连续和价值连续的周期信号
公开(公告)号：US07880655B2
公开(公告)日：2011-02-01
申请号：US12458934
申请日：2009-07-28
申请人： Andreas Danner , Thomas Fleischmann
发明人： Andreas Danner , Thomas Fleischmann
IPC分类号： H03M3/00
CPC分类号： H03M3/498 , H03M3/43
摘要： A system is disclosed, in particular for digitizing a time-continuous and value-continuous periodic signal with a respective firmly predefined number of samples per period. In at least one embodiment, the system includes an A/D converter for digitizing an analog AC signal applied to the input of the A/D converter, the converter including a single-bit modulator which converts the AC signal into a first data stream of temporally immediately successive single-bit data words at a predefined operating clock rate; and a downstream decimation filter which respectively aggregates a predefined number of temporally immediately successive single-bit data words in the first data stream into respective temporally immediately successive n-bit data words which form a second data stream which corresponds to a digitization of the AC signal at a sampling frequency which is derived from the operating clock rate and the predefined number by way of division. In order to achieve digitization with a respective firmly predefined number of samples per period with relatively little technical complexity, it is proposed in at least one embodiment that the operating clock rate be respectively generated by a digitally adjustable oscillator on the basis of a signal characteristic of the AC signal.
摘要翻译：公开了一种系统，特别是用于以每个周期以相应的牢固预定数量的采样数字化时间连续和价值连续的周期信号。在至少一个实施例中，该系统包括用于数字化施加到A / D转换器的输入的模拟AC信号的A / D转换器，该转换器包括将AC信号转换成第一数据流的单位调制器以预定的操作时钟速率在时间上立即连续的单位数据字; 以及下行抽取滤波器，其分别将第一数据流中的预定数量的时间上紧邻的单位数据字聚合成相应的时间上紧邻的n比特数据字，其形成对应于AC信号的数字化的第二数据流以通过划分的方式从操作时钟速率和预定数量导出的采样频率。为了以相对较少的技术复杂度以每个周期的相应的牢固预定数量的样本实现数字化，在至少一个实施例中提出了工作时钟速率分别基于数字可调振荡器的信号特性交流信号。

6. 发明申请

US20040037386A1 Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter 失效
标题翻译：用于调整delta-sigma变压器和/或开关电容滤波器的步进时钟的方法和系统
公开(公告)号：US20040037386A1
公开(公告)日：2004-02-26
申请号：US10399790
申请日：2003-04-22
发明人： Heikki Laamanen
IPC分类号： H03K021/00
CPC分类号： H03L7/0993 , H03H19/004 , H03M3/372 , H03M3/498
摘要： The invention relates to a method and system for implementing a digitally controlled sample and timing clock in a system performing analog and digital signal processing. According to the method, as the timing clock of the digital signal processing is used a clock with a controllable frequency such that said digital signal processing can have a factions suited for controlling the frequency of said timing clock, and the conversion of the signal is performed in synchronism with the timing clock of the digital signal processing operation when a delta-sigma converter or a switched-capacitor filter device is employed. According to the invention, the timing and sample clocks are generated by dividing a fixed-frequency clock operating at a frequency substantially higher than that of said timing/sample clock by a digital divider of an integer division factor whose division factor is controlled by means of an at least second-order delta-sigma modulator capable of delivering an output signal of two values so that one of the modulator output signal values selects the division factor to be N while the other value selects the division factor to be Nnull1, and, further, the delta-sigma modulator controlling the integer-factor divider is adapted to be clocked by the timing signal generated by said integer-factor divider.
摘要翻译：本发明涉及在执行模拟和数字信号处理的系统中实现数字控制采样和定时时钟的方法和系统。根据该方法，由于数字信号处理的定时时钟使用具有可控频率的时钟，使得所述数字信号处理可以具有适合于控制所述定时时钟的频率的系数，并且执行信号的转换与采用Δ-Σ转换器或开关电容滤波器装置的数字信号处理操作的定时时钟同步。根据本发明，定时和采样时钟是通过将工作在基本上高于所述定时/采样时钟的频率的固定频率时钟除以整数分频因子的数字分频器而产生的，其分频因子通过能够输出两个值的输出信号的至少二阶Δ-Σ调制器，使得一个调制器输出信号值选择分频因子为N，而另一个值选择分频因子为N + 1，以及此外，控制整数因子分频器的Δ-Σ调制器适于由所述整数因子分频器产生的定时信号计时。

7. 发明授权

US09525428B2 Randomly sampling reference ADC for calibration 有权
标题翻译：随机采样参考ADC进行校准
公开(公告)号：US09525428B2
公开(公告)日：2016-12-20
申请号：US14955905
申请日：2015-12-01
申请人： ANALOG DEVICES, INC.
发明人： Siddharth Devarajan , Eric Otte , Nevena Rakuljic , Carroll C. Speir
IPC分类号： H03M1/12 , H03M1/10 , H03M1/46 , H03M3/00
CPC分类号： H03M1/128 , H03M1/1019 , H03M1/1028 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/46 , H03M1/462 , H03M1/468 , H03M3/382 , H03M3/498
摘要： Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.
摘要翻译：模数转换器（ADC）可能会产生可能影响其性能的错误。为了提高性能，已经使用许多技术来补偿或纠正错误。当ADC采用亚微米技术实现时，ADC可以轻松轻松配备一个片上微处理器，用于执行各种数字功能。片上微处理器和任何合适的数字电路可以实现减少这些错误的功能，从而能够减少某些不必要的伪像，并为高度可配置的ADC提供灵活的平台。片上微处理器对于随机时间交织ADC特别有用。此外，随机采样ADC可以并行添加到主ADC用于校准目的。此外，整个系统可以包括用于校正ADC中的错误的有效实现。

8. 发明授权

US07916055B2 Sigma-delta modulator and method thereof 有权
标题翻译： Sigma-delta调制器及其方法
公开(公告)号：US07916055B2
公开(公告)日：2011-03-29
申请号：US12468049
申请日：2009-05-18
申请人： Kuo-Hsin Chen
发明人： Kuo-Hsin Chen
IPC分类号： H03M3/00
CPC分类号： H03M3/498
摘要： A sigma-delta modulator includes an adder, a filter, a quantizer, and a clock rate controller. The adder receives an input signal and an output signal to generate a summation signal. The filter is coupled to the adder and filters the summation signal to generate a filtered signal. The quantizer is coupled to the filter as well as the adder and quantizes the filtered signal to generate the output signal according to a first clock signal. The clock rate controller is coupled to the quantizer and generates the first clock signal, wherein a frequency of the first clock signal is variable.
摘要翻译： Σ-Δ调制器包括加法器，滤波器，量化器和时钟速率控制器。加法器接收输入信号和输出信号以产生求和信号。滤波器耦合到加法器并对求和信号进行滤波以产生滤波信号。量化器耦合到滤波器以及加法器，并对滤波信号进行量化，以根据第一时钟信号产生输出信号。时钟速率控制器耦合到量化器并产生第一时钟信号，其中第一时钟信号的频率是可变的。

9. 发明申请

US20080079617A1 IMPLANTABLE MEDICAL DEVICE WITH ADJUSTABLE SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION CLOCK RATE 有权
标题翻译：具有可调整SIGMA-DELTA模拟数字转换时钟速率的可植入医疗设备
公开(公告)号：US20080079617A1
公开(公告)日：2008-04-03
申请号：US11536942
申请日：2006-09-29
申请人： Mark A. Frigaard , Michael W. Heinks , Joel A. Anderson , Robert H. Mehregan
发明人： Mark A. Frigaard , Michael W. Heinks , Joel A. Anderson , Robert H. Mehregan
IPC分类号： H03M1/66
CPC分类号： H03M3/32 , A61N1/3704 , H03M3/498
摘要： An implantable medical device, such as a pacemaker or implantable cardioverter defibrillator, uses digital signal processing channels to process sensed time varying signals representing cardiac activity. Each digital signal processing channels includes a sigma-Delta analog-to-digital converter. The clock rate of each sigma-delta analog-to-digital converter is controlled as a function of a signal detection threshold for its respective digital signal processing channel. For higher threshold levels, a reduced clock rate for the sigma-delta analog-to-digital converter results in reduced power consumption and longer battery life.
摘要翻译：可植入医疗装置，例如起搏器或植入式心律转复除颤器，使用数字信号处理通道来处理表示心脏活动的感测时变信号。每个数字信号处理通道包括一个Σ-Δ模数转换器。每个Σ-Δ模数转换器的时钟速率被控制为其相应的数字信号处理通道的信号检测阈值的函数。对于更高的阈值电平，Σ-Δ模数转换器的降低的时钟频率导致功耗降低并延长电池寿命。

10. 发明申请

US20070236376A1 METHODS AND APPARATUS FOR SIGMA-DELTA MODULATOR HAVING SELECTABLE OSR WITH OPTIMAL RESONATOR COEFFICIENT 有权
标题翻译：具有最佳谐振器系数的可选择OSR的SIGMA-DELTA调制器的方法和装置
公开(公告)号：US20070236376A1
公开(公告)日：2007-10-11
申请号：US11745094
申请日：2007-05-07
申请人： Mucahit Kozak , Eugene Michael Petilli
发明人： Mucahit Kozak , Eugene Michael Petilli
IPC分类号： H03M3/02
CPC分类号： H03M3/498 , H03M3/448
摘要： A programmable Sigma-Delta Modulator (SDM) includes a first input to select an oversampling rate (OSR), which has a corresponding resonator coefficient value to provide an optimal notch in the Noise Transfer Function (NTF).
摘要翻译：可编程Σ-Δ调制器（SDM）包括用于选择过采样率（OSR）的第一输入端，其具有对应的谐振器系数值，以提供噪声传递函数（NTF）中的最佳陷波。

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