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1. 发明授权

US09991990B1 Sequence detection 有权
公开(公告)号：US09991990B1
公开(公告)日：2018-06-05
申请号：US15616954
申请日：2017-06-08
申请人： International Business Machines Corporation
发明人： Giovanni Cherubini , Roy Cideciyan , Simeon Furrer , Marcel Kossel , Hazar Yüksel
IPC分类号： H03M13/41 , H04L1/00 , H04L25/03
CPC分类号： H04L1/0054 , H03M13/413 , H03M13/4169 , H04L1/0052 , H04L25/03235
摘要： Calculating path metrics, associated with respective states of an n-state trellis, by accumulating branch metrics in a sequence detector. Each path metric is represented by N bits plus a wrap-around bit for indicating wrap-around of the N-bit value of that path metric.

2. 发明授权

US09571232B2 System and method for faster than Nyquist transmission 有权
标题翻译：系统和方法快于奈奎斯特传输
公开(公告)号：US09571232B2
公开(公告)日：2017-02-14
申请号：US14212735
申请日：2014-03-14
申请人： Huawei Technologies Co., Ltd.
发明人： Javad Abdoli , Ming Jia
IPC分类号： H04W4/00 , H04L1/00 , H04L1/20 , H04L25/03 , H04J11/00
CPC分类号： H04L1/006 , H04J11/00 , H04L1/0047 , H04L1/0052 , H04L1/0054 , H04L1/20 , H04L25/03203 , H04L25/03235 , H04L25/03305 , H04L25/03331 , H04L2025/03796
摘要： A method for operating a receiving device includes determining reliability ratings for undecoded data streams in a received transmission, selecting an undecoded data stream in the received transmission in accordance with the determined reliability ratings, thereby producing a selected data stream, and decoding the selected data stream with a decoding trellis, thereby producing a data symbol. The method also includes updating the decoding trellis in accordance with the data symbol, and repeating the selecting, the decoding, and the updating for remaining undecoded data streams in the received transmission.
摘要翻译：一种用于操作接收设备的方法包括：根据所确定的可靠性等级，确定所接收的传输中的未编码的数据流的可靠性等级，根据所确定的可靠性等级来选择未解码的数据流，从而产生所选择的数据流，并对所选择的数据流进行解码具有解码网格，从而产生数据符号。该方法还包括根据数据符号来更新解码网格，并重复对所接收的传输中剩余的未编码数据流的选择，解码和更新。

3. 发明授权

US08345784B2 Reduced-complexity equalization with sphere decoding 有权
标题翻译：通过球体解码进行降低复杂度均衡
公开(公告)号：US08345784B2
公开(公告)日：2013-01-01
申请号：US12479081
申请日：2009-06-05
申请人： Ali S. Khayrallah
发明人： Ali S. Khayrallah
IPC分类号： H04L5/12
CPC分类号： H04L25/03242 , H04L25/03235 , H04L27/2602 , H04L2025/03426
摘要： Techniques for spherical decision-feedback sequence estimation are disclosed. A received signal is equalized by forming a trellis comprising a plurality of stages, each stage corresponding to a symbol time and comprising a plurality of nodes, each having a node state. A most likely received symbol sequence is identified by evaluating cumulative state metrics for the nodes according to MLSE or DFSE criteria. The trellis is formed by selecting a set of fan-out branches for each node by identifying, of all possible state transition branches from the node to successor nodes in the succeeding stage, those state transition branches that have a spherical branch metric less than a pre-determined metric limit, and determining the cumulative state metric for each node as a function of the cumulative state metrics for predecessor nodes in the preceding stage and the spherical branch metrics for fan-out branches connecting the predecessor nodes to the node.
摘要翻译：公开了球面判决反馈序列估计技术。通过形成包括多个级的网格来均衡接收的信号，每个级对应于符号时间，并且包括多个节点，每个节点具有节点状态。通过根据MLSE或DFSE标准评估节点的累积状态度量来识别最可能的接收符号序列。通过从节点到后继阶段的后继节点的所有可能的状态转移分支，通过选择一组扇出分支来形成每个节点，这些状态转移分支具有小于预先的球面分支度量并且确定每个节点的累积状态度量作为前一级中的前导节点的累积状态度量的函数，以及用于将先前节点连接到节点的扇出分支的球面分支度量。

4. 发明授权

US08116366B2 Delayed decision feedback sequence estimator 有权
标题翻译：延迟决策反馈序列估计器
公开(公告)号：US08116366B2
公开(公告)日：2012-02-14
申请号：US12149157
申请日：2008-04-28
申请人： Toshitsugu Kawashima , Mark Horowitz
发明人： Toshitsugu Kawashima , Mark Horowitz
IPC分类号： H03H7/30 , H03K5/159
CPC分类号： H04L25/03057 , H04L25/03235
摘要： Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.
摘要翻译：公开了一种延迟判定反馈序列估计器，其包括延迟判定反馈序列估计器主单元，该延迟判定反馈序列估计器主单元包括DDFSE计算单元组，其包括（L + M）DDFSE计算单元，其数量等于多个块中的每一个的长度，其中接收的数据符号序列分为其中（L + M）DDFSE计算单元以流水线配置连接以并行地执行块的延迟判定反馈序列估计; 以及边缘效应检测和校正电路，其检测由于处理分离块的延迟的判定反馈序列估计的边缘效应并校正相关的位错误。

5. 发明授权

US08094707B1 List-based detection in fading channels with long intersymbol interference 有权
标题翻译：基于列表的检测在具有长码间干扰的衰落信道中
公开(公告)号：US08094707B1
公开(公告)日：2012-01-10
申请号：US12029922
申请日：2008-02-12
申请人： SaiRamesh Nammi , Deva K. Borah
发明人： SaiRamesh Nammi , Deva K. Borah
IPC分类号： H03H7/30
CPC分类号： H04L25/03267 , H04L25/03235 , H04L2025/0342
摘要： An apparatus, computer software, and method for data detection in channels suffering from intersymbol interference comprising receiving a signal representative of a binary digit of data, computing a reliability score for that binary digit of data via windowed Chase equalization, and based on the reliability score, causing a signal to be output that the binary digit is a zero or a one.
摘要翻译：一种用于在遭受码间干扰的信道中进行数据检测的装置，计算机软件和方法，包括接收表示数据的二进制数字的信号，通过窗口Chase均衡计算数据的二进制数字的可靠性得分，并且基于可靠性得分，导致输出信号，二进制数字为零或一。

6. 发明申请

US20110211661A1 Metrics Calculations Utilizing Pre-Stored Values 有权
标题翻译：使用预存值的指标计算
公开(公告)号：US20110211661A1
公开(公告)日：2011-09-01
申请号：US13106616
申请日：2011-05-12
申请人： Cyril Valadon
发明人： Cyril Valadon
IPC分类号： H04L27/06
CPC分类号： H04L25/03292 , H04L25/03184 , H04L25/03235
摘要： A trellis processing technique for estimating a transmitted signal from a received signal acquired through a channel achieves a reduced computational structure when implementing a DDFSE-like branch metrics calculation by pre-storing computed values, which can be re-used. The technique involves storing differences between a received symbol and different products, each of which is a product of a channel coefficient corresponding to a least time delay and a different possible transmitted symbol. A summation of products is calculated, each product being a product of a possible transmitted signal symbol and a channel coefficient other than the channel coefficient corresponding to the least time delay, the summation being specific to a branch-start state in a trellis. The summation is combined with different stored differences in a calculation of branch metrics leading to different branch-end states in the trellis.
摘要翻译：用于通过信道获取的接收信号估计发射信号的网格处理技术通过预先存储可重新使用的计算值来实现类似DDFSE的分支量度计算，实现了减少的计算结构。该技术涉及存储接收符号和不同产品之间的差异，每个产品是与最小时间延迟对应的信道系数与不同可能发送符号的乘积。计算产品的总和，每个产品是可能的传输信号符号的乘积和不同于最小时间延迟的信道系数的通道系数，该总和特定于网格中的分支开始状态。总和与不同的存储差异结合在分支度量的计算中，导致网格中不同的分支结束状态。

7. 发明授权

US07801240B2 Multi-pair gigabit ethernet transceiver 有权
标题翻译：多对千兆以太网收发器
公开(公告)号：US07801240B2
公开(公告)日：2010-09-21
申请号：US12273436
申请日：2008-11-18
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04B15/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

8. 发明授权

US07656959B2 Pipelined decision-feedback unit in a reduced-state viterbi detector with local feedback 有权
标题翻译：在具有本地反馈的简化状态维特比检测器中的流水线判决反馈单元
公开(公告)号：US07656959B2
公开(公告)日：2010-02-02
申请号：US10962188
申请日：2004-10-08
申请人： Erich Franz Haratsch
发明人： Erich Franz Haratsch
IPC分类号： H04L5/12 , H04L23/02
CPC分类号： H04L25/03235 , H03M13/03 , H04L25/03057 , H04L25/4917
摘要： A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.
摘要翻译：公开了一种流水线判决反馈单元（DFU），用于具有本地反馈的简化状态维特比检测器。所公开的流水线判决反馈单元通过基于部分符号间干扰的估计的流水线计算提高了通过简化状态维特比检测器可以实现的最大数据速率。因此公开了流水线判决反馈单元，其计算多个基于部分符号间干扰的估计，其中至少一个部分符号间干扰估计基于所选择的部分符号间干扰估计; 并且将所选择的部分符号间干扰估计从用于路径扩展的部分符号间干扰估计中选择为状态。

9. 发明申请

US20090296791A1 Multi-Pair Gigabit Ethernet Transceiver 失效
标题翻译：多对千兆以太网收发器
公开(公告)号：US20090296791A1
公开(公告)日：2009-12-03
申请号：US12534614
申请日：2009-08-03
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04B1/38
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

10. 发明授权

US07570701B2 Multi-pair gigabit ethernet transceiver 有权
公开(公告)号：US07570701B2
公开(公告)日：2009-08-04
申请号：US11999175
申请日：2007-12-04
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H04B15/00
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

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