专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20170358881A1 ELECTRICAL CONTACT PAD FOR ELECTRICALLY CONTACTING A CONNECTOR 审中-公开
公开(公告)号：US20170358881A1
公开(公告)日：2017-12-14
申请号：US15617735
申请日：2017-06-08
申请人： TE CONNECTIVITY CORPORATION
发明人： GRAHAM HARRY SMITH, JR. , SCOTT ERIC WALTON , MICHAEL FRANK CINA
IPC分类号： H01R12/72 , H05K1/02 , H05K1/11
CPC分类号： H01R12/721 , H01P5/028 , H01R13/112 , H05K1/025 , H05K1/0251 , H05K1/115 , H05K1/117 , H05K2201/0776 , H05K2201/09381 , H05K2201/09481 , H05K2201/09618 , H05K2201/09672 , H05K2201/09727 , H05K2201/0979
摘要： An electrical contact pad for electrically contacting a connector includes first, second and third regions. The first region is connected to a trace. The second region is adjacent to the first region and has a width less than the first region. The third region is adjacent to the second region and has a width that is greater than the second region. The third region is sized to make contact with a connector. Having the width of the second region be smaller than the width of the first and third regions increases an impedance of the electrical contact pad.

2. 发明申请

US20170245366A1 DUAL PRINTED CIRCUIT BOARD ASSEMBLY, PRINTED CIRCUIT BOARD AND MODULAR PRINTED CIRCUIT BOARD 审中-公开
公开(公告)号：US20170245366A1
公开(公告)日：2017-08-24
申请号：US15222969
申请日：2016-07-29
申请人： Wistron NeWeb Corp.
发明人： Cheng-Hsien Hsu , Chih-Yuan Chiang , Cheng-Huang Chen
IPC分类号： H05K1/14 , H05K1/11 , G01R31/28 , H05K1/02
CPC分类号： H05K1/144 , G01R31/2812 , G01R31/2818 , H05K1/0268 , H05K1/11 , H05K2201/042 , H05K2201/0776
摘要： A dual printed circuit board assembly, a printed circuit board, and a modular printed circuit board are provided. The printed circuit board includes a plurality of first connection points. The modular printed circuit board includes a plurality of second connection points. The modular printed circuit board is adapted to be mounted on the printed circuit board and includes a sensing unit, a first detecting unit, and a first notifying unit. The sensing unit outputs a detecting voltage according to a contact state between the first connection points and the second connection points. The first detecting unit determines whether the first connection points are respectively connected to the corresponding second connection points according to the detecting voltage. When one of the first connection points is not connected to the corresponding one of the second connection points, the first detecting unit controls the first notifying unit to issue a notification.

3. 发明申请

US20150313005A1 PRINTED CIRCUIT BOARD 审中-公开
标题翻译：印刷电路板
公开(公告)号：US20150313005A1
公开(公告)日：2015-10-29
申请号：US14406913
申请日：2012-06-15
申请人： Masashi TAKABATAKE , Kenji KASHIWAGI
发明人： Masashi TAKABATAKE , Kenji KASHIWAGI
IPC分类号： H05K1/02 , H05K1/11
CPC分类号： H05K1/0213 , H05K1/025 , H05K1/0253 , H05K1/111 , H05K3/3421 , H05K2201/0776 , H05K2201/09372 , H05K2201/0969 , H05K2201/10189 , Y02P70/611
摘要： [Object] There is suggested a printed circuit board capable of realizing impedance matching by securing joint reliability between signal pins of a surface mount connector and signal pin pads and preventing the reduction of impedance of signal pin pads while minimizing the reduction of a wirable area.[Solution] A printed circuit board equipped with a signal pin pad, which is soldered to a signal pin from a surface mount connector, and a ground layer located as a lower layer below the signal pin pad; wherein a fillet is formed around a joint area between the signal pin and the signal pin pad after soldering; wherein a cut-out portion is provided in the signal pin pad within a joint area with the signal pin; and wherein the size of the cut-out portion is set within the range of being completely covered within the joint area with the signal pin based on size tolerance of the signal pin, fabrication tolerance of the printed circuit board, and mount position tolerance of the surface mount connector.
摘要翻译：提出了一种印刷电路板，其能够通过确保表面安装连接器的信号引脚和信号引脚焊盘之间的连接可靠性来实现阻抗匹配，并且防止信号引脚焊盘的阻抗减小，同时最小化可吸收区域的减少。 [解决方案]配备有从表面安装连接器焊接到信号引脚的信号引脚焊盘的印刷电路板和位于信号引脚焊盘下方的下层的接地层; 其中在焊接之后，在信号引脚和信号引脚焊盘之间的接合区域周围形成圆角; 其中在与所述信号引脚的接合区域内的所述信号引脚焊盘中设置切口部分; 并且其中，根据信号引脚的尺寸公差，印刷电路板的制造公差以及印刷电路板的安装位置公差，将切除部分的尺寸设定在与信号销的接合区域内完全覆盖的范围内表面贴装连接器。

4. 发明申请

US20180192517A1 APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS 审中-公开
公开(公告)号：US20180192517A1
公开(公告)日：2018-07-05
申请号：US15854598
申请日：2017-12-26
申请人： Micron Technology, Inc.
发明人： Atsushi Morishima
IPC分类号： H05K1/11 , H05K1/18
CPC分类号： H05K1/115 , H05K1/025 , H05K1/114 , H05K1/181 , H05K2201/0776 , H05K2201/09227 , H05K2201/09309 , H05K2201/09609 , H05K2201/0979
摘要： Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

5. 发明授权

US09888574B1 Apparatus and methods for via connection with reduced via currents 有权
公开(公告)号：US09888574B1
公开(公告)日：2018-02-06
申请号：US15399664
申请日：2017-01-05
申请人： Micron Technology, Inc.
发明人： Atsushi Morishima
IPC分类号： H05K7/00 , H05K1/11 , H05K1/18
CPC分类号： H05K1/115 , H05K1/025 , H05K1/114 , H05K1/181 , H05K2201/0776 , H05K2201/09227 , H05K2201/09309 , H05K2201/09609 , H05K2201/0979
摘要： Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

6. 发明申请

US20160192477A1 Conductive Transparent Substrate Manufacturing Method, and Conductive Transparent Substrate 有权
标题翻译：导电透明基板制造方法和导电透明基板
公开(公告)号：US20160192477A1
公开(公告)日：2016-06-30
申请号：US14902980
申请日：2014-07-07
申请人： INKTEC Co., Ltd.
发明人： Kwang-Choon Chung , Ji Hoon Yoo , Joonki Seong , Byung Hun Kim , Nam Boo Cho , Myung-Bong Yoo
IPC分类号： H05K1/02 , H05K3/00 , H05K1/09 , H05K3/12 , H05K3/06 , H05K1/03
CPC分类号： H05K1/0274 , G06F3/041 , G06F2203/04103 , H01L51/445 , H05K1/0213 , H05K1/0289 , H05K1/0298 , H05K1/0306 , H05K1/032 , H05K1/034 , H05K1/0346 , H05K1/097 , H05K3/0026 , H05K3/06 , H05K3/067 , H05K3/12 , H05K3/1258 , H05K2201/0776 , Y02E10/549 , Y02P70/521
摘要： Provided herein is a method for manufacturing a conductive transparent substrate, the method including forming a plurality of main electrodes on the substrate such that the main electrodes are distanced from one another; and forming a connecting electrode that electrically connects two or more main electrodes such that the plurality of main electrodes are grouped into a plurality of group electrodes that are electrically disconnected from one another, thereby producing a conductive transparent substrate with excellent transmittance in a process of high yield.
摘要翻译：本发明提供一种制造导电透明基板的方法，该方法包括在基板上形成多个主电极，使得主电极彼此间隔开; 以及形成连接两个或多个主电极的连接电极，使得所述多个主电极被分组成彼此电断开的多个组电极，从而在高过程中产生具有优异透射率的导电透明基板产量。

7. 发明授权

US09622344B2 Multilayer wiring board with enclosed Ur-variant dual conductive layer 有权
公开(公告)号：US09622344B2
公开(公告)日：2017-04-11
申请号：US14391748
申请日：2013-02-28
申请人： KABUSHIKI KAISHA NIHON MICRONICS
发明人： Tatsuo Inoue , Takayasu Sugai , Toshiyuki Kudo , Toshinori Omori
IPC分类号： H05K1/02 , H05K3/46 , H05K1/09
CPC分类号： H05K1/0298 , H05K1/0233 , H05K1/0242 , H05K1/025 , H05K1/09 , H05K3/46 , H05K2201/0154 , H05K2201/0338 , H05K2201/0391 , H05K2201/0776 , H05K2201/0792 , H05K2201/083 , Y10T29/49155
摘要： A multi-layer wiring board includes wiring layers stacked on a substrate with an insulating layer between each layer. A wire formed in the wiring layer consists of a first layer and a second layer to form a double layered structure. The first layer is made of a first conductive material and the second layer is made of a second conductive material having relative magnetic permeability of 10 or more and larger than that of the first conductive material. The characteristic impedance of the wire is adjusted to a value closer to 50 ohms than that of a wire which has the same thickness as of the wire with the double layered structure, and is made only of the first conductive material.

8. 发明授权

US09572252B2 Wiring substrate and method of manufacturing wiring substrate 有权
标题翻译：接线基板及制造布线基板的方法
公开(公告)号：US09572252B2
公开(公告)日：2017-02-14
申请号：US14444135
申请日：2014-07-28
申请人： TOPPAN PRINTING CO., LTD. , NATIONAL UNIVERSITY CORPORATION GUNMA UNIVERSITY
发明人： Tetsuyuki Tsuchida , Toshikazu Okubo , Ikuo Shohji , Takahiro Kano
IPC分类号： B05D5/12 , B28B19/00 , C23C18/00 , H01C17/06 , H05K3/00 , H05K1/09 , C23C18/36 , C23C18/44 , C23C18/16 , H05K3/24 , C23C18/50
CPC分类号： H05K1/09 , C23C18/1651 , C23C18/36 , C23C18/44 , C23C18/50 , H05K3/243 , H05K3/244 , H05K2201/032 , H05K2201/0776 , H05K2203/072
摘要： A wiring substrate includes an electrode including Cu or a Cu alloy, and a plated film including an electroless nickel-plated layer formed on the electrode and an electroless gold-plated layer formed on the electroless nickel-plated layer. The electroless nickel-plated layer is formed by co-precipitation of Ni, P, Bi, and S, the electroless nickel-plated layer includes a content of P of 5% by mass or more and less than 10% by mass, a content of Bi of 1 ppm by mass to 1,000 ppm by mass, and a content of S of 1 ppm by mass to 2,000 ppm by mass, and a mass ratio of the content of S to the content of Bi (S/Bi) is more than 1.0.
摘要翻译：布线基板包括包含Cu或Cu合金的电极和形成在电极上的化学镀镍层和形成在化学镀镍层上的化学镀金层的镀膜。化学镀镍层通过Ni，P，Bi和S的共沉淀形成，无电镀镍层的P含量为5质量％以上且小于10质量％，含量的Bi为1质量ppm〜1000质量ppm，S为1质量ppm〜2000质量ppm，S含量与Bi（S / Bi）含量的质量比为更多比1.0。

9. 发明申请

US20140332259A1 WIRING SUBSTRATE AND METHOD OF MANUFACTURING WIRING SUBSTRATE 有权
标题翻译：接线基板和制造接线基板的方法
公开(公告)号：US20140332259A1
公开(公告)日：2014-11-13
申请号：US14444135
申请日：2014-07-28
申请人： TOPPAN PRINTING CO., LTD. , NATIONAL UNIVERSITY CORPORATION GUNMA UNIVERSITY
发明人： Tetsuyuki TSUCHIDA , Toshikazu OKUBO , Ikuo SHOHJI , Takahiro KANO
IPC分类号： H05K1/09 , C23C18/36 , H05K3/24
CPC分类号： H05K1/09 , C23C18/1651 , C23C18/36 , C23C18/44 , C23C18/50 , H05K3/243 , H05K3/244 , H05K2201/032 , H05K2201/0776 , H05K2203/072
摘要： A wiring substrate includes an electrode including Cu or a Cu alloy, and a plated film including an electroless nickel-plated layer formed on the electrode and an electroless gold-plated layer formed on the electroless nickel-plated layer. The electroless nickel-plated layer is formed by co-precipitation of Ni, P, Bi, and S, the electroless nickel-plated layer includes a content of P of 5% by mass or more and less than 10% by mass, a content of Bi of 1 ppm by mass to 1,000 ppm by mass, and a content of S of 1 ppm by mass to 2,000 ppm by mass, and a mass ratio of the content of S to the content of Bi (S/Bi) is more than 1.0.
摘要翻译：布线基板包括包含Cu或Cu合金的电极和形成在电极上的化学镀镍层和形成在化学镀镍层上的化学镀金层的镀膜。化学镀镍层通过Ni，P，Bi和S的共沉淀形成，无电镀镍层的P含量为5质量％以上且小于10质量％，含量的Bi为1质量ppm〜1000质量ppm，S为1质量ppm〜2000质量ppm，S含量与Bi（S / Bi）含量的质量比为更多比1.0。

10. 发明申请

US20190098855A1 APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS 审中-公开
公开(公告)号：US20190098855A1
公开(公告)日：2019-04-04
申请号：US16192673
申请日：2018-11-15
申请人： MICRON TECHNOLOGY, INC.
发明人： Atsushi Morishima
IPC分类号： A01H5/10 , C12N15/82 , A01H6/54 , A01H1/02
CPC分类号： A01H5/10 , A01H1/02 , A01H6/542 , C12N15/8245 , C12N15/8247 , C12N15/8251 , C12N15/8271 , C12N15/8274 , C12N15/8275 , C12N15/8278 , C12N15/8279 , C12N15/8286 , C12N15/8289 , H05K1/025 , H05K1/114 , H05K1/115 , H05K1/181 , H05K2201/0776 , H05K2201/09227 , H05K2201/09309 , H05K2201/09609 , H05K2201/0979
摘要： Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式