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1. 发明授权

US07180116B2 Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor 有权
标题翻译：自对准金属电极消除金属绝缘子半导体（MIS）电容器的自然氧化效应
公开(公告)号：US07180116B2
公开(公告)日：2007-02-20
申请号：US10861148
申请日：2004-06-04
申请人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
发明人： Min-Hsiung Chiang , Chih-Ta Wu , Tsung-Hsun Huang
IPC分类号： H01L27/108
CPC分类号： H01L27/0629 , H01L27/1085 , H01L27/10867 , H01L29/6659
摘要： A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.
摘要翻译：一种形成电容器的方法，包括以下步骤。在电容器区域中的衬底上形成初始电容器，由此衬底的一部分使得初始电容器与隔离浅沟槽隔离（STI）结构分离。性传播感染在结构上形成第一介电层。将第一电介质层图案化为：形成遮蔽复合电容器的部分; 并且暴露STI和至少部分将初步电容器与浅沟槽隔离结构分开的衬底部分。金属部分至少形成在衬底部分上。在图案化的第一介电层部分，金属部分和STI上形成第二电介质层，由此至少在衬底部分上形成的金属部分防止在至少衬底部分上形成自然氧化物。本发明还包括由此形成的结构。

2. 发明申请

US20060057803A1 Method to reduce a capacitor depletion phenomena 有权
标题翻译：降低电容器耗尽现象的方法
公开(公告)号：US20060057803A1
公开(公告)日：2006-03-16
申请号：US11264447
申请日：2005-11-01
申请人： Min-Hsiung Chiang
发明人： Min-Hsiung Chiang
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion of the insulator layer in an STI region is recessed below the top surface of the semiconductor substrate exposing a bare, tapered side of the semiconductor substrate. Ion implantation into the tapered side of the portion of semiconductor substrate exposed in the recessed STI portion, as well as into a top portion of semiconductor substrate located adjacent to the recessed STI portion, results in formation of a capacitor region now greater in surface area than a counterpart capacitor region which is formed via implantation into only a top portion of semiconductor substrate. Growth of a gate insulator layer and definition of gate structures in the logic device region, also simultaneously forms a capacitor dielectric layer on the underlying capacitor region, as well as a capacitor plate structure in the capacitor cell region.
摘要翻译：已经开发了集成电容器单元和逻辑器件区域的制造的方法，其中电容器区域的表面积增加，并且电容器耗尽现象的风险降低。在形成具有锥形侧面的绝缘体填充的STI区域之后，STI区域中的绝缘体层的一部分在半导体衬底的顶表面下方露出，露出半导体衬底的裸露的锥形侧。离子注入到暴露在凹陷STI部分中的半导体衬底的部分的锥形侧以及位于邻近凹陷STI部分的半导体衬底的顶部部分中，导致形成电容器区域现在表面积大于通过仅注入半导体衬底的顶部形成的对应电容器区域。栅极绝缘体层的生长和逻辑器件区域中栅极结构的定义也同时在下面的电容器区域上形成电容器电介质层，以及电容器单元区域中的电容器板结构。

3. 发明申请

US20050151180A1 Method to reduce a capacitor depletion phenomena 审中-公开
标题翻译：降低电容器耗尽现象的方法
公开(公告)号：US20050151180A1
公开(公告)日：2005-07-14
申请号：US10754835
申请日：2004-01-09
申请人： Min-Hsiung Chiang
发明人： Min-Hsiung Chiang
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10894
摘要： A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion of the insulator layer in an STI region is recessed below the top surface of the semiconductor substrate exposing a bare, tapered side of the semiconductor substrate. Ion implantation into the tapered side of the portion of semiconductor substrate exposed in the recessed STI portion, as well as into a top portion of semiconductor substrate located adjacent to the recessed STI portion, results in formation of a capacitor region now greater in surface area than a counterpart capacitor region which is formed via implantation into only a top portion of semiconductor substrate. Growth of a gate insulator layer and definition of gate structures in the logic device region, also simultaneously forms a capacitor dielectric layer on the underlying capacitor region, as well as a capacitor plate structure in the capacitor cell region.
摘要翻译：已经开发了集成电容器单元和逻辑器件区域的制造的方法，其中电容器区域的表面积增加，并且电容器耗尽现象的风险降低。在形成具有锥形侧面的绝缘体填充的STI区域之后，STI区域中的绝缘体层的一部分在半导体衬底的顶表面下方露出，露出半导体衬底的裸露的锥形侧。离子注入到暴露在凹陷STI部分中的半导体衬底的部分的锥形侧以及位于邻近凹陷的STI部分的半导体衬底的顶部部分中，导致形成电容器区域现在表面积大于通过仅注入半导体衬底的顶部形成的对应电容器区域。栅极绝缘体层的生长和逻辑器件区域中栅极结构的定义也同时在下面的电容器区域上形成电容器电介质层，以及电容器单元区域中的电容器板结构。

4. 发明申请

US20050056885A1 Dual poly layer and method of manufacture 有权
标题翻译：双层多层及其制造方法
公开(公告)号：US20050056885A1
公开(公告)日：2005-03-17
申请号：US10662609
申请日：2003-09-15
申请人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
发明人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
IPC分类号： H01L21/8239 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L29/76
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , Y10S257/903 , Y10S257/904
摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.
摘要翻译：提供了具有双重多晶硅电极的半导体器件和制造方法。半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。每个多晶硅层可以单独掺杂。该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

5. 发明授权

US06849387B2 Method for integrating copper process and MIM capacitor for embedded DRAM 失效
标题翻译：用于集成嵌入式DRAM的铜工艺和MIM电容器的方法
公开(公告)号：US06849387B2
公开(公告)日：2005-02-01
申请号：US10081479
申请日：2002-02-21
申请人： Min-Hsiung Chiang , Chi-Hsin Lo
发明人： Min-Hsiung Chiang , Chi-Hsin Lo
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/532 , H01L21/8238
CPC分类号： H01L23/5223 , H01L21/76808 , H01L21/76838 , H01L23/53238 , H01L27/10852 , H01L27/10882 , H01L27/10894 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A method for integrating copper with an MIM capacitor during the formation the MIM capacitor. The MIM capacitor is generally formed upon a substrate and at least one copper layer is deposited upon the substrate and layers thereof to form at least one metal layer from which the MIM capacitor is formed, such that the MIM capacitor may be adapted for use with an embedded DRAM device. The MIM capacitor comprises a low-temperature MIM capacitor. At least one DRAM crown photo layer may be formed upon the substrate and layers thereof to form the MIM capacitor. The number of additional lithographic steps required in BEOL manufacturing operations is thus only one, while the capacitance of the MIM capacitor can be improved greatly because the sequential process of the DRAM crown photo patterning steps may be altered.
摘要翻译：在MIM电容器形成期间，将铜与MIM电容器集成的方法。 MIM电容器通常形成在衬底上，并且至少一个铜层沉积在衬底及其层上以形成MIM电容器形成的至少一个金属层，使得MIM电容器可适用于嵌入式DRAM设备。 MIM电容器包括低温MIM电容器。可以在衬底及其层上形成至少一个DRAM冠光敏层以形成MIM电容器。因此，在BEOL制造操作中所需的附加光刻步骤的数量仅为一个，而MIM电容器的电容可以大大提高，因为可以改变DRAM冠光栅图案化步骤的顺序处理。

6. 发明授权

US06818495B1 Method for forming high purity silicon oxide field oxide isolation region 失效
标题翻译：形成高纯氧化硅场氧化物隔离区的方法
公开(公告)号：US06818495B1
公开(公告)日：2004-11-16
申请号：US09325951
申请日：1999-06-04
申请人： Min-Hsiung Chiang , Jin-Yuan Lee , Jenn Ming Huang
发明人： Min-Hsiung Chiang , Jin-Yuan Lee , Jenn Ming Huang
IPC分类号： H01L218238
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/32 , H01L21/76202
摘要： A method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a silicon oxide dielectric layer. There is provided a silicon semiconductor substrate. There is formed upon the silicon semiconductor substrate a blanket silicon oxide pad oxide layer. There is then formed upon the pad oxide layer a patterned silicon nitride masking layer delineating active regions of the silicon semiconductor substrate from isolation regions. There is formed upon the isolation regions by thermal oxidation of the semiconductor silicon substrate in a dry oxidizing environment at an elevated temperature a thick silicon oxide dielectric layer employed as a field oxide (FOX) dielectric isolation layer formed through the silicon nitride patterned masking layer. There is then stripped from the silicon semiconductor substrate the patterned silicon nitride layer, permitting fabrication of microelectronics structures within and upon the semiconductor silicon substrate employing thick silicon oxide field oxide (FOX) dielectric isolation regions without foreign phases or inhomogeneities formed in the “bird's beak” region therein.
摘要翻译：一种在微电子制造中采用的硅半导体衬底内形成氧化硅介电层的方法。提供硅半导体衬底。在硅半导体衬底上形成覆盖氧化硅衬垫氧化物层。然后在焊盘氧化物层上形成图案化的氮化硅掩模层，其从隔离区域描绘硅半导体衬底的有源区。通过半导体硅衬底在干燥的氧化环境中在高温下通过热氧化形成隔离区，厚氧化硅介电层用作通过氮化硅图案化掩模层形成的场氧化物（FOX）电介质隔离层。然后从硅半导体衬底剥离图案化氮化硅层，允许在半导体硅衬底内和之上制造微电子结构，其中采用厚的氧化硅场氧化物（FOX）电介质隔离区，在“鸟喙”中形成无异相或不均匀性 “区域。

7. 发明授权

US06436762B1 Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins 有权
标题翻译：使用湿式回蚀技术改善DRAM电路上电容器电气故障的位线的方法，以改善位线电容器覆盖边界
公开(公告)号：US06436762B1
公开(公告)日：2002-08-20
申请号：US09855238
申请日：2001-05-14
申请人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
发明人： Kuo-Chyuan Tzeng , Tse-Liang Ying , Min-Hsiung Chiang , Hsiao-Hui Tseng , Chung-Wei Chang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/8234 , H01L21/20
CPC分类号： H01L27/10888 , H01L27/10811 , H01L28/91
摘要： A method is described for making capacitor-under-bit line (CUB) DRAM cells with improved overlay margins between bit lines and capacitor top electrodes. After forming FETs for the memory cells, an interpolysilicon oxide (IPO) layer is deposited, and first and second plug contacts are formed in the IPO to the FET source/drain areas for capacitors and bit line contacts, respectively. A capacitor node oxide is deposited, and first openings are etched in which crown capacitor bottom electrodes are formed. After etching back the node oxide a thin interelectrode dielectric layer is formed and a conformal conducting layer is deposited to form capacitor top electrodes. A photoresist mask is used to etch openings in the conducting layer over the second plug contacts, and an isotropic etch is used to recess the openings under the mask to increase the spacing between the capacitor top electrodes and the bit line contacts to improve the overlay margin. The photoresist mask is removed and an interlevel dielectric (ILD) layer is deposited. Bit-line contact openings are etched in the ILD layer aligned over the recessed openings and in the node oxide to the second contact plugs. Bit-line contact plugs are formed extending through the recessed openings, and a first conducting layer is deposited and patterned to form bit lines and to complete the memory cells for the DRAM.
摘要翻译：描述了一种用于制造具有改进的位线和电容器顶部电极之间的覆盖边缘的电容器下位线（CUB）DRAM单元的方法。在形成用于存储单元的FET之后，沉积多晶硅氧化物（IPO）层，并且在IPO中分别将第一和第二插头触点形成到用于电容器和位线触点的FET源极/漏极区域。沉积电容器节点氧化物，并且蚀刻第一开口，其中形成冠电容器底部电极。在蚀刻回节点氧化物之后，形成薄的电极间电介质层，并且淀积保形导电层以形成电容器顶部电极。使用光致抗蚀剂掩模来蚀刻导电层上的第二插头触点上的开口，并且使用各向同性蚀刻来凹陷掩模下方的开口以增加电容器顶部电极和位线触点之间的间隔，以改善覆盖边缘。去除光致抗蚀剂掩模并沉积层间电介质（ILD）层。在ILD层中蚀刻位线接触开口，其在凹入的开口上以及在节点氧化物中对齐到第二接触插塞。位线接触插塞形成为延伸穿过凹入的开口，并且第一导电层被沉积和图案化以形成位线并且完成用于DRAM的存储单元。

8. 发明授权

US06274426B1 Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure 有权
标题翻译：自对准接触工艺为冠状动态随机存取存储器电容器结构
公开(公告)号：US06274426B1
公开(公告)日：2001-08-14
申请号：US09257830
申请日：1999-02-25
申请人： Yu-Hua Lee , James (Cheng-Ming) Wu , Min-Hsiung Chiang
发明人： Yu-Hua Lee , James (Cheng-Ming) Wu , Min-Hsiung Chiang
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/31116 , H01L21/3212 , H01L21/76802 , H01L21/76897 , H01L27/10855 , H01L28/91
摘要： A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repairing, or filling, seams or voids, that may be present in the thick silicon oxide layer, at the perimeter of the SAC opening, via formation of a silicon nitride spacer on the sides of the SAC opening. Subsequent processing features: the isotropic removal of a top portion of the silicon nitride spacer; the formation of a polysilicon storage node structure, in the SAC opening; and the recessing of a top portion of the thick silicon oxide layer, resulting in exposure of additional polysilicon storage node, surface area.
摘要翻译：已经开发了一种用于制造位于SAC开口的底部的壁上的具有氮化硅间隔物的SAC开口中的冠状电容器结构的方法。该工艺特征是在厚的氧化硅层中形成SAC开口，然后通过形成氮化硅间隔物在SAC开口的周边处形成可能存在于厚氧化硅层中的或者填充接缝或空隙在SAC开幕的两边。随后的处理特征：氮化硅间隔物的顶部的各向同性去除; 形成多晶硅存储节点结构，在SAC开放; 并且厚的氧化硅层的顶部凹陷，导致额外的多晶硅存储节点的曝光，表面积。

9. 发明授权

US07208369B2 Dual poly layer and method of manufacture 有权
标题翻译：双层多层及其制造方法
公开(公告)号：US07208369B2
公开(公告)日：2007-04-24
申请号：US10662609
申请日：2003-09-15
申请人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
发明人： Chih-Yang Pai , Min-Hsiung Chiang , Chen-Jong Wang , Shou-Gwo Wuu
IPC分类号： H01L21/8242
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/1087 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , Y10S257/903 , Y10S257/904
摘要： Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.
摘要翻译：提供了具有双重多晶硅电极的半导体器件和制造方法。半导体器件包括沉积在第二多晶硅层上的第一多晶硅层。每个多晶硅层可以单独掺杂。该方法还允许晶片上的一些半导体器件具有单个多晶硅晶片和其它器件以具有双重多晶硅层。在一个实施例中，半导体器件用于形成存储器件，其中位于单元区域中的存储电容器和晶体管形成双重多晶硅层，并且外围区域中的器件形成有单个多晶硅层。

10. 发明申请

US20050112876A1 Method to form a robust TiCI4 based CVD TiN film 审中-公开
标题翻译：形成坚固的TiCI4基CVD TiN膜的方法
公开(公告)号：US20050112876A1
公开(公告)日：2005-05-26
申请号：US10723237
申请日：2003-11-26
申请人： Chih-Ta Wu , Kuo Yin Lin , Min-Hsiung Chiang
发明人： Chih-Ta Wu , Kuo Yin Lin , Min-Hsiung Chiang
IPC分类号： C23C16/34 , C23C16/56 , H01L21/20 , H01L21/768
CPC分类号： C23C16/56 , C23C16/34 , H01L21/76843 , H01L21/76856 , H01L21/76862
摘要： A method is described for a plasma treatment of a TiCl4 based CVD deposited TiN layer that reduces stress, lowers resistivity, and improves film stability. Resistivity is stable in an air ambient for up to 48 hours after the plasma treatment. A TiN layer is treated with a N-containing plasma that includes N2, NH3, or N2H4 at a temperature between 500° C. and 700° C. Optionally, H2 may be added to N2 in the plasma step which removes chloride impurities and densifies the TiN layer. The TiN layer may serve as a barrier layer, an ARC layer, or as a bottom electrode in a MIM capacitor. An improved resistance of the treated TiN layer to oxidation during formation of an oxide based insulator layer and a lower leakage current in the MIM capacitor is also achieved.
摘要翻译：描述了一种用于等离子体处理基于TiCl 4的CVD沉积TiN层的方法，其降低应力，降低电阻率并提高膜的稳定性。等离子体处理后电阻率在空气环境中稳定长达48小时。用含N的等离子体处理TiN层，该等离子体包括N 2，NH 3或N 2 H 4，在500℃至700℃之间的温度下，可以在等离子体步骤中将H 2 N加入到N 2 N中，除去氯化物杂质并致密化 TiN层。 TiN层可以用作MIM电容器中的阻挡层，ARC层或底电极。还实现了在形成氧化物基绝缘体层期间处理的TiN层对氧化的改善的电阻和MIM电容器中较低的漏电流。

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