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1. 发明授权

US11251781B2 Dynamic D flip-flop, data operation unit, chip, hash board and computing device 有权
公开(公告)号：US11251781B2
公开(公告)日：2022-02-15
申请号：US17045276
申请日：2019-05-07
申请人： CANAAN CREATIVE CO., LTD.
发明人： Jieyao Liu , Nangeng Zhang , Jingjie Wu , Shenghou Ma
IPC分类号： H03K3/356 , H03K3/35 , H03K3/86 , H03K19/00
摘要： The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

2. 发明授权

US4607172A Bipolar strobed transistor latch for a high gain comparator 失效
标题翻译：用于高增益比较器的双极选通晶体管锁存器
公开(公告)号：US4607172A
公开(公告)日：1986-08-19
申请号：US579636
申请日：1984-02-13
申请人： Thomas M. Frederiksen , Daniel D. Culmer
发明人： Thomas M. Frederiksen , Daniel D. Culmer
IPC分类号： H03K3/2885 , H03K3/35 , H03K3/356
CPC分类号： H03K3/2885
摘要： A differential amplifier is combined with a latch in a stage suitable for use in high speed comparators. An IC topography for the latch is also shown.
摘要翻译：差分放大器与适用于高速比较器的级中的锁存器组合。还示出了用于闩锁的IC形状。

3. 发明授权

US4260909A Back gate bias voltage generator circuit 失效
标题翻译：背栅偏压发生电路
公开(公告)号：US4260909A
公开(公告)日：1981-04-07
申请号：US937951
申请日：1978-08-30
申请人： Austin C. Dumbri , Walter Rosenzweig
发明人： Austin C. Dumbri , Walter Rosenzweig
IPC分类号： G05F3/20 , G11C11/407 , G11C11/413 , G11C11/417 , H01L21/822 , H01L27/04 , H03K3/011 , H03K3/356 , H03K3/35 , H03K3/353 , H03L1/00
CPC分类号： G05F3/205 , G11C11/417 , H01L27/04 , H03K3/011 , H03K3/356008
摘要： A back gate bias voltage generator circuit consists of three MOS transistors (Q4, Q5, Q6) with a separate load element (Q1, Q2, Q3) coupled to the drain of each and a voltage clamp (Q7) connected to an output terminal (16). A terminal at the potential of a power supply (VCC) serves as one input and a terminal at the substrate potential (VSub) serves as another input. When the power supply (VCC) potential and the substrate potential are within normal operating ranges, the output terminal (16) assumes a reference potential (VSS). The potential of the output terminal increases in magnitude if either of the two input potentials (VSS, VSub) goes outside preselected operating ranges.
摘要翻译：背栅偏置电压发生器电路由三个MOS晶体管（Q4，Q5，Q6）组成，具有耦合到每个的漏极的单独的负载元件（Q1，Q2，Q3）和连接到输出端子的电压钳（Q7） 16）。电源电位（VCC）的端子用作一个输入，并且在衬底电位（VSub）上的端子用作另一个输入。当电源（VCC）电位和衬底电位在正常工作范围内时，输出端（16）呈现参考电位（VSS）。如果两个输入电位（VSS，VSub）中的任一个超出了预选的工作范围，输出端子的电位就会增加。

4. 发明授权

US4185253A Temperature sensitive relaxation oscillator 失效
标题翻译：温度敏感放大振荡器
公开(公告)号：US4185253A
公开(公告)日：1980-01-22
申请号：US946178
申请日：1978-09-27
申请人： Robert W. Lade , Stanley V. Jaskolski , Gordon B. Spellman , Herman P. Schutten
发明人： Robert W. Lade , Stanley V. Jaskolski , Gordon B. Spellman , Herman P. Schutten
IPC分类号： G01K7/00 , G01K3/00 , G01K7/01 , H01L29/74 , H03K3/352 , H03K3/35
CPC分类号： G01K3/005 , G01K7/01 , H03K3/352
摘要： A temperature sensitive thyristor is incorporated in a relaxation oscillator to provide active temperature sensing. As temperature decreases, the breakover voltage V.sub.BO of the thyristor increases, and when V.sub.BO becomes greater than the supply voltage, oscillations will cease, thus providing a low temperature alarm point. As temperature increases, V.sub.BO decreases and the amplitude of oscillation diminishes, thus providing a high temperature alarm point. This is a "fail-safe" arrangement because component failure also provides a warning condition (absence of oscillation). Frequency of oscillation may also be sensed as an indication of temperature.
摘要翻译：温度敏感晶闸管被并入松弛振荡器中以提供有源温度感测。随着温度的降低，晶闸管的跳变电压VBO增加，当VBO变得大于电源电压时，振荡将停止，从而提供低温报警点。随着温度升高，VBO减小，振荡幅度减小，从而提供高温报警点。这是一个“故障安全”的安排，因为组件故障也提供了一个警告条件（没有振荡）。振动频率也可以被感测为温度的指示。

5. 发明授权

US4161703A Schmitt trigger square wave oscillator 失效
标题翻译：施密特触发方波振荡器
公开(公告)号：US4161703A
公开(公告)日：1979-07-17
申请号：US886395
申请日：1978-03-14
申请人： Karl-Diether Nutz
发明人： Karl-Diether Nutz
IPC分类号： H03K3/03 , H03K3/295 , H03K3/35
CPC分类号： H03K3/03
摘要： An oscillator for producing rectangular pulses comprises a Schmitt trigger controlled by an R.C. element connected in series, a constant current source for charging up the capacitor and a current image circuit for ensuring that the discharge current of the capacitor is consistent with its charging current.
摘要翻译：用于产生矩形脉冲的振荡器包括由R.C.控制的施密特触发器。串联连接的元件，用于对电容器充电的恒流源和用于确保电容器的放电电流与其充电电流一致的当前图像电路。

6. 发明授权

US4103258A Pulse generator including a capacitor which is discharged through a thyristor 失效
标题翻译：脉冲发生器包括通过一个电容器放电的电容器
公开(公告)号：US4103258A
公开(公告)日：1978-07-25
申请号：US778217
申请日：1977-03-16
申请人： Takahiko Iida , Yasunobu Arita
发明人： Takahiko Iida , Yasunobu Arita
IPC分类号： F23Q3/00 , H03K3/3525 , H03K4/84 , H03K3/35
CPC分类号： F23Q3/004 , H03K3/3525 , H03K4/84
摘要： A pulse generating circuit is provided by charging from a DC power source through charging resistor to a capacitor; detecting the preset value of the charging condition of the capacitor; discharging the charge of the capacitor through a main thyristor by triggering the main thyristor and generating a pulse output to a load by the discharging current. The pulse generating circuit comprises a shunt circuit for dividing the voltage of the DC power source beside the circuit for charging the capacitor whereby the potential of the shunt point is compared with the charged voltage of the capacitor through a three terminal trigger element and the trigger element is turned on when the charged voltage of the capacitor becomes substantially equal to the voltage of the DC power source to obtain the trigger output of the main thyristor.

7. 发明授权

US4071780A Transient generator 失效
标题翻译：瞬态发生器
公开(公告)号：US4071780A
公开(公告)日：1978-01-31
申请号：US722282
申请日：1976-09-10
申请人： Ronald H. Burnett
发明人： Ronald H. Burnett
IPC分类号： G01R27/28 , G01R31/00 , H03L7/06 , H03K5/15 , H03K3/35 , H03K5/01
CPC分类号： G01R31/001 , G01R27/28 , H03L7/06
摘要： A transient generator for testing the susceptibility of, particularly, digital equipment to noise and the efficacy of filter designs in removing it. The device is adapted for capacitative coupling to the equipment and employs digital circuitry for the control of the output transient.
摘要翻译：一种瞬态发生器，用于测试特别是数字设备对噪声的敏感性，以及滤波器设计在去除噪声方面的功效。该器件适用于与设备的电容耦合，并采用数字电路来控制输出瞬变。

8. 发明授权

US3742373A Pulse generators 失效
标题翻译：脉冲发生器
公开(公告)号：US3742373A
公开(公告)日：1973-06-26
申请号：US3742373D
申请日：1971-11-05
申请人： PERKIN ELMER LTD
发明人： ARMSTRONG J , TENNANT M
IPC分类号： H02M1/08 , H03K3/35 , H03K1/02 , H03K1/16
CPC分类号： H02M1/083 , H03K3/35
摘要： A trigger pulse generator circuit for controlling, for example, an AC thyristor system which in turn controllably supplies a final device (e.g., an electrical heater for a temperaturecontrolled oven), in which the relative number of pulses supplied (of the maximum possible during a given period) is proportional to the input (''''demand'''') signal. Thus the supply to the final device is quantitatively proportional to the measured demand (e.g., by a temperature sensor), thereby causing close tracking of the desired condition (e.g., temperature). In fact, the entire system may be operated in the ''''open loop'''' mode since the supply inherently tends to match quantitatively the required amount (i.e., the ''''demand'''') to cause the final device to reach a desired setpoint. In closed loop operation, excursions of the effect of the final device from the setpoint are smaller than with existing systems using nonquantitatively supplied pulses where any time lag in the sensor relative to the condition will tend to cause ''''overshoot'''' (e.g., too many pulses before the sensor responds to the change).
摘要翻译：触发脉冲发生器电路，用于控制例如AC可控硅系统，AC系统可控制地提供最终装置（例如，用于温度控制的炉的电加热器），其中提供的脉冲的相对数量（最大可能的在给定时段内）与输入（“需求”）信号成比例。因此，最终装置的供给量与所测量的需求成比例（例如，通过温度传感器），从而导致所需条件（例如，温度）的紧密跟踪。事实上，整个系统可以在“开环”模式下操作，因为供给固有地倾向于定量地匹配所需量（即“需求”），以使最终设备达到期望的设定点。在闭环操作中，最终装置从设定点的影响的偏移小于使用非量计提供的脉冲的现有系统，其中传感器相对于该条件的任何时间滞后将倾向于引起“过冲”（例如，太多的脉冲在传感器响应变化之前）。

9. 发明授权

US3740730A Latchable decoder driver and memory array 失效
标题翻译：可编解码器驱动器和存储阵列
公开(公告)号：US3740730A
公开(公告)日：1973-06-19
申请号：US3740730D
申请日：1971-06-30
申请人： IBM
发明人： HO I , JEN T
IPC分类号： G11C8/10 , G11C11/414 , G11C11/415 , H03K3/35 , H03K17/00 , H03K17/62 , H03K17/73 , G11C7/00
CPC分类号： G11C11/415 , G11C8/10 , G11C11/414 , H03K3/35 , H03K17/6221 , H03K17/73 , H03K2217/0036
摘要： A monolithic memory comprising an array of semiconductor storage cells and a plurality of decoders for accessing information to the storage cells during a given duty cycle. Reduced power consumption is achieved by the application of addressing signals to the decoder input lines for a given time period less than the accessing duty cycle in order to attain full duty cycle activating signals on the decoder output lines for accessing the memory array, and also by virtue of the selected address input lines associated with a selected decoder not drawing current during the given time period.
摘要翻译：一种单片存储器，包括半导体存储单元阵列和用于在给定占空比期间向存储单元访问信息的多个解码器。通过在小于访问占空比的给定时间周期内对解码器输入线应用寻址信号来实现降低的功耗，以便在解码器输出线上获得用于访问存储器阵列的全占空比激活信号，并且还通过所选择的地址输入线与所选择的解码器相关联，在给定时间段期间不绘制电流。

10. 发明授权

US3643235A Monolithic semiconductor memory 失效
标题翻译：单片半导体存储器
公开(公告)号：US3643235A
公开(公告)日：1972-02-15
申请号：US3643235D
申请日：1969-12-05
申请人： IBM
发明人： BERGER HORST H , WIEDMANN SIGFRIED K
IPC分类号： G11C11/411 , G11C15/00 , H01L21/00 , H01L27/00 , H01L27/07 , H01L27/082 , H01L27/10 , H01L27/102 , H03K3/286 , H03K3/288 , H03K3/35 , G11C11/40 , H03K3/281
CPC分类号： H03K3/35 , G11C11/4113 , G11C11/4116 , G11C15/00 , H01L21/00 , H01L27/00 , H01L27/0744 , H01L27/0821 , H01L27/0828 , H01L27/10 , H01L27/1022 , H01L27/1025 , H03K3/286 , H03K3/288
摘要： This specification discloses a storage cell which employs inversely operated and transverse transistors to reduce storage cell size accessing times and power consumption when the cell is fabricated in monolithic form. Two cross-connected transistors are inversely operated so that they share a common emitter region with a separate base region and collector region for each of the cross-connected transistors. In this way, the transistors can be fabricated in a single diffusion region. The collector of each of the cross-connected transistors is connected to the collector of a load transistor of the opposite type transistor and to the base of an addressing transistor having its emitter connected to the sense line and its collector connected to the base of the load transistors. The two addressing and load transistors are formed in a single isolation zone with collector and base regions of the addressing transistors serving also as the base and collector regions respectively of the load transistors which are fabricated as transverse transistors with a common emitter region.
摘要翻译：本说明书公开了一种存储单元，其使用反向操作和横向晶体管来减小当单元以单体形式制造存储单元尺寸时的存取时间和功耗。两个交叉连接的晶体管被反向工作，使得它们共享具有用于每个交叉连接的晶体管的单独的基极区域和集电极区域的公共发射极区域。以这种方式，可以在单个扩散区域中制造晶体管。每个交叉连接的晶体管的集电极连接到相对型晶体管的负载晶体管的集电极，并连接到寻址晶体管的基极，其发射极连接到感测线，其集电极连接到负载的基极晶体管。两个寻址和负载晶体管形成在单个隔离区域中，寻址晶体管的集电极和基极区域也分别用作负载晶体管的基极和集电极区域，这些区域被制造为具有公共发射极区域的横向晶体管。

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