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1. 发明授权

US4794627A Process for the parallel-series code conversion of a parallel digital train and a device for the transmission of digitized video signals using such a process 失效
标题翻译：用于并行数字列的并行序列代码转换的处理和用于使用这种处理传输数字化视频信号的设备
公开(公告)号：US4794627A
公开(公告)日：1988-12-27
申请号：US326546
申请日：1981-12-02
申请人： Jean L. Grimaldi
发明人： Jean L. Grimaldi
IPC分类号： H03M7/14 , H04L25/49 , H04N7/00 , H04N7/56 , H04L3/00
CPC分类号： H04N7/56 , H04L25/4906 , H04L25/4908
摘要： The process for the code conversion of eight parallel bits into words with nine series bits uses among the nine-bit words on the one hand those having five "1" and four "0" and which do not have five consecutive bits and whereof none starts or finishes with four identical bits, as well as their complements to 1, and on the other words having six "1" and three "0" with a maximum of transitions, as well as their complements to 1. Two complementary digital frame synchronization words are chosen from among the nine-bit words not retained for coding and which are not found in a random series of coded words.
摘要翻译：八位并行位代码转换为9位的字的过程一方面使用九位字，一方面具有五个“1”和四个“0”，并且没有五个连续的位，哪些没有启动或完成四个相同的位，以及它们与1的补码，另一个字有六个“1”和三个“0”，最大的转换，以及它们的补码为1.两个互补的数字帧同步字从不保留用于编码的九位字中选择，并且在随机的一系列编码字中找不到。

2. 发明授权

US4539680A Chip to chip information bit transmission process and device 失效
标题翻译：芯片到芯片信息位传输过程和设备
公开(公告)号：US4539680A
公开(公告)日：1985-09-03
申请号：US556803
申请日：1983-12-01
申请人： Gerard Boudon , Pierre Mollier , Gerard Lebesherais
发明人： Gerard Boudon , Pierre Mollier , Gerard Lebesherais
IPC分类号： H04L25/38 , H04L25/45 , H04L25/48 , H04L25/49 , H04J3/06 , H04L3/00 , H04L25/34
CPC分类号： H04L25/45 , H04L25/49
摘要： In the transmitting chip, the bits are serialized and applied to a coding circuit in which bit stream (D) and its complement (D) are transformed into two signals (PH1 and PH2) under the control of a saw-tooth clock signal CK'. Signals (PH1 and PH2) are sent to the receiving chip, wherein they are applied to a decoding circuit which generates two signals (DJ) and (DK) representative of the data bits and a recovered clock signal CLK. The three signals (DJ, DK and CLK) as well as a frame signal (F) are used by a converting and demultiplexing circuit for assembling bytes of parallel data bits.
摘要翻译：在发送芯片中，将这些比特序列化并应用于编码电路，其中，在锯齿时钟信号CK的控制下，比特流（D）及其补码（＆amp; upbar＆D）被变换成两个信号（PH1和PH2） '。信号（PH1和PH2）被发送到接收芯片，其中它们被应用于产生表示数据位的两个信号（＆amp; upbar＆D）和（＆amp; upbar＆D）的解码电路和恢复的时钟信号CLK。三个信号（＆upbar＆D，＆upbar＆D和CLK）以及帧信号（F）由转换和解复用电路用于组合并行数据位的字节。

3. 发明授权

US4506252A Ternary data encoding system 失效
标题翻译：三元数据编码系统
公开(公告)号：US4506252A
公开(公告)日：1985-03-19
申请号：US511044
申请日：1983-07-05
申请人： George V. Jacoby , Martin Cohn
发明人： George V. Jacoby , Martin Cohn
IPC分类号： H03M5/16 , H04L25/49 , H04L3/00
CPC分类号： H04L25/4923 , H03M5/16
摘要： Apparatus and method for encoding binary data in a ternary format including ternary 0, ternary 1 and ternary 2 code symbols. In a preferred embodiment of the invention utilized for magnetic data storage, a ternary 0 is represented by the absence of signal change, a ternary 1 is represented by a single transition and a ternary 2 is represented by a pulse or pair of closely spaced transitions. Further features of the invention provide for merging ternary code symbols so as to prevent the spacing between adjacent symbols from becoming so small as to create undesirable crowding, and inserting and shifting symbols to prevent the spacing between adjacent symbols from becoming so great as to adversely affect recovery of the encoded data.
摘要翻译：用于以三进制格式编码二进制数据的装置和方法，包括三进制0，三进制1和三进制代码符号。在用于磁数据存储的本发明的优选实施例中，三元0由不存在信号变化表示，三元1由单个转换表示，并且三进制2由脉冲或一对紧密间隔的转换表示。本发明的另外的特征提供了合并三进制代码符号，以便防止相邻符号之间的间隔变得如此小以致产生不期望的拥挤，以及插入和移位符号以防止相邻符号之间的间隔变得如此大以致不利地影响恢复编码数据。

4. 发明授权

US4476347A Method and circuit arrangement for transmitting communication signals between switching centers of first and second switching networks operating with different transmission procedures 失效
标题翻译：用于在以不同传输程序操作的第一和第二交换网络的交换中心之间发送通信信号的方法和电路装置
公开(公告)号：US4476347A
公开(公告)日：1984-10-09
申请号：US472979
申请日：1983-03-08
申请人： Rolf Hagen , Peter Weidner
发明人： Rolf Hagen , Peter Weidner
IPC分类号： H04L12/50 , H04L29/06 , H04L3/00 , H04L23/00
CPC分类号： H04L29/06 , H04L12/50
摘要： A method and a circuit arrangement are provided for the transmission of communication signals over switching centers of a first switching network and of a second switching network operating with different transmission procedures. The transmission is executed with the assistance of a decentralized converter in which a fixed assignment between the transmission lines of the first switching network and the virtual channels to be employed on transmission lines of the second switching center for a signal transmission is defined. Of the signals to be transmitted, only the signal portions effecting the execution of network-dependent procedure divisions are converted in the converter. The data signals appearing in accordance with the network-independent procedure divisions are combined in unaltered form with the converted signal portions.
摘要翻译：提供了一种方法和电路装置，用于通过第一交换网络的交换中心和以不同传输过程操作的第二交换网络的通信信号的传输。在分散式转换器的协助下执行传输，其中定义了在第一交换网络的传输线和用于信号传输的第二交换中心的传输线路上采用的虚拟信道之间的固定分配。在要发送的信号中，转换器中仅转换执行与网络相关的过程划分的信号部分。根据与网络无关的程序划分出现的数据信号以未改变的形式与转换的信号部分组合。

5. 发明授权

US4431864A Communications system input-output converter 失效
标题翻译：通信系统输入输出转换器
公开(公告)号：US4431864A
公开(公告)日：1984-02-14
申请号：US311471
申请日：1981-10-14
申请人： Norman J. Sturdevant, Jr.
发明人： Norman J. Sturdevant, Jr.
IPC分类号： H04L12/02 , H04L11/02 , H04L3/00
CPC分类号： H04L12/02
摘要： An input-output converter permits the integration of terminals and transmit and receive equipments that operate at given logic voltage levels and character formats into communications system that operate at different logic voltage levels and character formats. The input-output converter includes a universal asynchronous receiver transmitter that converts m bit serial data into n bit parallel data in a receive mode and n bit parallel data to m bit serial data in a transmit mode while stripping and adding asynchronous start-stop bits. The input-output converter also includes logic voltage level converters that convert digital data to appropriate logic voltage levels for each function.
摘要翻译：输入 - 输出转换器允许终端的集成，以及将以给定逻辑电压电平和字符格式工作的设备发送和接收到以不同逻辑电压电平和字符格式工作的通信系统。输入 - 输出转换器包括一个通用异步接收器发送器，它将M位串行数据转换为接收模式的n位并行数据，并在发送模式下将n位并行数据转换为m位串行数据，同时剥离和添加异步启动 - 停止位。输入/输出转换器还包括逻辑电压电平转换器，可将数字数据转换为适用于每个功能的逻辑电压电平。

6. 发明授权

US4298773A Method and system for 5-bit encoding of complete Arabic-Farsi languages 失效
标题翻译：完整的阿拉伯语 - 波斯语的5位编码的方法和系统
公开(公告)号：US4298773A
公开(公告)日：1981-11-03
申请号：US109943
申请日：1980-01-07
申请人： Khaled M. Diab
发明人： Khaled M. Diab
IPC分类号： B41J3/01 , H04L17/00 , B41J5/00 , H04L3/00
CPC分类号： B41J3/01 , H04L17/00
摘要： A method and apparatus for coding, transmitting, receiving, and displaying remotely or locally, all Arabic-Farsi characters or letters, basic arithmetic signs, numerals, punctuation marks and diacritical marks, as well as teleprinter operation commands in 5-bit standard Baudot codes. An Arabic-Farsi teleprinter similar in operation to the English teleprinter and compatible with the International exchange systems is provided without eliminating any letter forms. The teleprinter operation (the ability to compress the data into 5-bit characters) is based upon two basic criteria of the Arabic-Farsi languages, namely: (1) the form (start, middle, end or independent) of a character can be known if the preceding character and the following characters are known; and (2) there are six characters that are identical except for the presence or absence of a dot. The digital logic circuits make use of the above criteria to permit the encoding and decoding and thus the transmitting and receiving of complete Arabic-Farsi alphabets. A particular grouping of characters with level coder for each grouping, as well as a keyboard arrangement and control circuits for more versatile use of input/output devices are also disclosed.
摘要翻译：用于远程或本地编码，发送，接收和显示所有阿拉伯语 - 波斯字符，基本算术符号，数字，标点符号和变音符号以及5位标准波特率代码中的电传打印机操作命令的方法和装置。提供类似于英国电传打印机并与国际交换系统兼容的阿拉伯语 - 波斯传播打印机，而不消除任何字母表格。电传打印机操作（将数据压缩为5位字符的能力）基于阿拉伯语 - 波斯语的两个基本标准，即：（1）字符的形式（开始，中间，结束或独立）可以是如果前面的字符和以下字符是已知的; 和（2）有六个字符是相同的，除了存在或不存在点。数字逻辑电路使用上述标准来允许编码和解码，从而允许完整的阿拉伯语 - 波斯语字母的发送和接收。还公开了用于每个分组的具有级别编码器的特定分组字符，以及用于更多功能地使用输入/输出设备的键盘布置和控制电路。

7. 发明授权

US4285062A Digital multi-level multi-phase modulation communication system 失效
标题翻译：数字多电平多相调制通信系统
公开(公告)号：US4285062A
公开(公告)日：1981-08-18
申请号：US79725
申请日：1979-09-28
申请人： Yasuharu Yoshida , Yoshimi Tagashira , Seijiro Yokoyama
发明人： Yasuharu Yoshida , Yoshimi Tagashira , Seijiro Yokoyama
IPC分类号： H04J9/00 , H04L27/02 , H04L27/18 , H04L27/22 , H04L27/34 , H04L27/36 , H04L27/38 , H04L3/00
CPC分类号： H04L27/02 , H04L27/362 , H04L27/3872
摘要： A digital multi-level multi-phase modulation system utilizes quaternary differential encoding and decoding of only the first two of N digital signal trains. A decision circuit is used to examine the frame pulses in one of the first two signal trains and in at least one of the remaining signal trains and generates output signals which can be used in a gate circuit to resolve the phase-lock ambiguity of the recovered carrier and thereby reproduce the original N signal trains.
摘要翻译：数字多电平多相调制系统仅使用N个数字信号序列中的前两个的四进制差分编码和解码。使用判定电路来检查前两个信号列之一和剩余信号列中的至少一个中的帧脉冲，并且产生输出信号，其可以在门电路中使用以解决所恢复的相位锁定模糊度从而再现原始的N信号列车。

8. 发明授权

US4271526A Three-level, self-clocked data transmission system 失效
标题翻译：三级自主时钟数据传输系统
公开(公告)号：US4271526A
公开(公告)日：1981-06-02
申请号：US45805
申请日：1979-06-05
申请人： Laurence P. Flora
发明人： Laurence P. Flora
IPC分类号： H04L25/49 , H04L25/40 , H04L3/00
CPC分类号： H04L25/4925
摘要： A serial digital data transmission system wherein pairs of binary input signals are encoded into a self-clocked three-level signal having high, low and intermediate levels for driving over a transmission line with level transitions occurring in response to an applied clock signal, and with a valid signal being employed to indicate data presence. Selectable encoding is provided in response to detecting any accumulated excess of high or low prior transmission levels so as to continually seek maintenance of an intermediate average level for the transmitted signal. The clock and valid signals are regenerated at the receiver for use in deriving the binary signal data from the received three-level signal.
摘要翻译：一种串行数字数据传输系统，其中二进制输入信号对被编码为具有高，低和中等电平的自时钟三电平信号，用于在传输线上驱动，响应于施加的时钟信号而发生电平转换，并且与用于指示数据存在的有效信号。响应于检测到高或低的先前传输电平的任何累积的过量而提供可选择的编码，以便连续地寻找所发送的信号的中间平均电平的维护。时钟和有效信号在接收机处再生，用于从接收的三电平信号中导出二进制信号数据。

9. 发明授权

US4209771A Code converting method and system 失效
标题翻译：代码转换方法和系统
公开(公告)号：US4209771A
公开(公告)日：1980-06-24
申请号：US943618
申请日：1978-09-19
申请人： Masachika Miyata , Eiichi Amada
发明人： Masachika Miyata , Eiichi Amada
IPC分类号： H03M5/20 , G06F7/68 , H03M1/00 , H03M7/00 , H04L25/49 , H04L3/00
CPC分类号： H03M7/3048 , G06F7/68
摘要： A code converting method in which a multivalue signal x.sub.i sampled at a sampling period of mT, where m (an even number) equals 2.sup.n (n being integer) and x.sub.i is non-negative integer not greater than m, is received and subjected to density conversion to be delivered out in the form of a train of m binary signals sampled at a sampling period of T. A Z-transform Y(Z) of the binary signal to be delivered out is expressed as, ##EQU1## where q.sub.i+1 .ident.q.sub.i +X.sub.i+1 +m, and mod 2; q.sub.o =0 and where H(x.sub.i, q.sub.i, Z) represents a polynomial of the order related to Z.sup.-1 not greater than (m-1) which has non-zero terms having each a coefficient of 1(one) and which satisfies H(k, q.sub.i, 1)=k, H(k, q.sub.i, Z)=Z.sup.-(m-1) H(k,q.sub.i,1/Z) and H(k,0,Z)=H(k,1,Z) for k being an even number, and H(k,0,Z)=Z.sup.-(m-1) H(k,1,1/Z) for k being an odd number.
摘要翻译：代码转换方法，其中以m（偶数）等于2n（n为整数）和xi为不大于m的非负整数的mT的采样周期采样的多值信号xi被接收并且经受密度转换为以T的采样周期采样的m个二进制信号串的形式传送。要传送的二进制信号的Z变换Y（Z）表示为，其中qi + 1 = qi + Xi + 1 + m，mod 2; qo = 0，其中H（xi，qi，z）表示与Z-1相关的次序的多项式不大于（m-1），其具有每个系数为1（1）的非零项，并且满足 H（k，qi，1）= k，H（k，qi，Z）= Z-（m-1）H（k，qi，1 / Z）和H（k，0，Z）= H ，1，Z），k为奇数，H（k，0，Z）= Z-（m-1）H（k，1,1 / Z）

10. 发明授权

US4206447A Adaptive quantizer apparatus for differential coding of nonuniform digital signals 失效
标题翻译：用于非均匀数字信号的差分编码的自适应量化器装置
公开(公告)号：US4206447A
公开(公告)日：1980-06-03
申请号：US28272
申请日：1979-04-09
申请人： Yau-Chau Ching , Ben-Zion Gotz
发明人： Yau-Chau Ching , Ben-Zion Gotz
IPC分类号： H03M3/04 , H03M7/00 , H04L3/00
CPC分类号： H03M3/042 , H03M7/3046
摘要： Known adaptive differential pulse code modulation (ADPCM) coders typically convert a nonuniform input signal to a linearized representation thereof prior to processing the signal. Usually the linearized signal requires more bits than the nonuniform signal. To mitigate the expense of apparatus for manipulating signals having many bits as well as to dissipate a scale size mistrack between the coder and a decoder, the instant ADPCM coder, responsive to an improved adaptive control signal, converts (300, 600) the nonuniform input signal to special semiuniform representation thereof which representation is processed (400, 500, 600) by the ADPCM coder. The semiuniform signal permits use of fewer bits than the prior art linearized representation. Also, the adaptive control signal is provided by a scale index generator including rounding-up and rounding-down means, for dissipating scale size mistrack. Further, the semiuniform signal permits much of the ADPCM process to be confined to relatively inexpensive read only memory (ROM) devices (300, 400, 500, 800).
摘要翻译：已知的自适应差分脉冲编码调制（ADPCM）编码器通常在处理信号之前将不均匀的输入信号转换成其线性化表示。通常，线性化信号比非均匀信号需要更多的位。为了减轻用于操纵具有多个位的信号的装置的费用以及消耗编码器和解码器之间的刻度尺度误差，本发明的ADPCM编码器响应于改进的自适应控制信号来转换（300,600）不均匀输入信号通过ADPCM编码器处理（400,500,600）的特殊的半均匀表示。半同步信号允许使用比现有技术的线性化表示更少的位。此外，自适应控制信号由包括四舍五入和舍入装置的比例指标发生器提供，用于消除尺度尺度的误差。此外，半均匀信号允许ADPCM过程的大部分被限制在相对便宜的只读存储器（ROM）设备（300,400,500,800）中。

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