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1. 发明申请

US20200334013A1 PROCESSING ELEMENT AND PROCESSING SYSTEM 审中-公开
公开(公告)号：US20200334013A1
公开(公告)日：2020-10-22
申请号：US16702099
申请日：2019-12-03
申请人： SK hynix Inc.
发明人： Jae-Hyeok JANG
IPC分类号： G06F7/492 , G06F7/50 , G06N3/063
摘要： A processing element may include a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and an accumulation circuit configured to accumulate a value of the filtered feature, wherein the pre-processing circuit comprises: a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight having a value of −1; and a zero filtering circuit configured to change a value of the weight to 0 when the feature having a value of 0.

2. 发明申请

US20210042088A1 CONDITION CODE ANTICIPATOR FOR HEXADECIMAL FLOATING POINT 有权
公开(公告)号：US20210042088A1
公开(公告)日：2021-02-11
申请号：US16536663
申请日：2019-08-09
申请人： International Business Machines Corporation
发明人： Silvia Melitta Mueller , Petra Leber , Kerstin Claudia Schelm , Cedric Lichtenau
IPC分类号： G06F7/499 , G06F7/492 , G06F7/483 , G06F9/30
摘要： An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

3. 发明授权

US11294628B2 Processing element and processing system 有权
公开(公告)号：US11294628B2
公开(公告)日：2022-04-05
申请号：US16702099
申请日：2019-12-03
申请人： SK hynix Inc.
发明人： Jae-Hyeok Jang
IPC分类号： G06F7/492 , G06F7/50 , G06F7/544 , G06N3/063
摘要： A processing element may include a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and an accumulation circuit configured to accumulate a value of the filtered feature, wherein the pre-processing circuit comprises: a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight having a value of −1; and a zero filtering circuit configured to change a value of the weight to 0 when the feature having a value of 0.

4. 发明授权

US08577952B2 Combined binary/decimal fixed-point multiplier and method 失效
标题翻译：组合二进制/十进制定点乘数和方法
公开(公告)号：US08577952B2
公开(公告)日：2013-11-05
申请号：US12329686
申请日：2008-12-08
申请人： Mark Alan Erle , Brian John Hickmann
发明人： Mark Alan Erle , Brian John Hickmann
IPC分类号： G06F7/492
CPC分类号： G06F7/491 , G06F2207/4915
摘要： A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations.
摘要翻译：使用BCD-4221重新编码为十进制数字的组合二进制/十进制定点乘数。这允许使用二进制进位保存硬件来执行小数加法与小修正。所描述的设计提供了改进的减少树组织以减少乘法器的面积和延迟以及利用冗余十进制编码的减少树组件的改进以帮助减少延迟。还引入了分解还原树架构，减少了二进制产品的延迟，总面积只有小的增加。提出了区域和延迟估计，表明所提出的设计对于单独的二进制和十进制乘法器具有显着的面积改进，同时对于十进制和二进制运算仍然保持类似的延迟。

5. 发明授权

US3986015A Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection 失效
标题翻译：用于数字数据处理器的算术单元，具有用于奇偶校验位产生和错误检测的改进系统
公开(公告)号：US3986015A
公开(公告)日：1976-10-12
申请号：US589298
申请日：1975-06-23
申请人： David N. Gooding , Everett M. Shimp
发明人： David N. Gooding , Everett M. Shimp
IPC分类号： G06F7/00 , G06F7/38 , G06F7/492 , G06F7/494 , G06F7/508 , G06F11/10 , H03M13/00 , H03K13/34 , H04L1/10
CPC分类号： G06F11/10 , G06F7/00
摘要： A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.
摘要翻译：一种采用二进制加法器的数字运算单元，用于以分区格式或打包格式对多位二进制编码十进制数进行加法和减法，并且具有为运算单元产生的结果数据字节产生奇偶校验位的改进方法。当使用二进制加法器对二进制编码十进制数进行加法或减法时，需要校正出现在二进制加法器的输出端的一些数据，以获得正确的结果。然而，本发明的奇偶校验位产生电路对于出现在加法器的输出端的未校正数据起作用，但是对于表示算术单元的最终输出的校正数据产生适当的奇偶校验位。这减少了以常规方式生成奇偶校验位的另外时间延迟的量。

6. 发明申请

US20220237440A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
公开(公告)号：US20220237440A1
公开(公告)日：2022-07-28
申请号：US17611207
申请日：2020-05-07
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hajime KIMURA , Munehiro KOZUMA
IPC分类号： G06N3/063 , H01L27/108 , G06F7/492 , G06F7/496 , H01L29/786
摘要： A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

7. 发明申请

US20220012306A1 INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM 有权
公开(公告)号：US20220012306A1
公开(公告)日：2022-01-13
申请号：US17486468
申请日：2021-09-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA DIGITAL SOLUTIONS CORPORATION
发明人： Masaru SUZUKI , Hayato Goto , Kosuke Tatsumura
IPC分类号： G06F17/16 , G06F7/58 , G06F7/492
摘要： An information processing device includes a storage unit and a processing circuit. The storage unit is configured to store a first variable and the second variable. The processing circuit is configured to update a first vector having the first variable by weighted addition of the corresponding second variable to the first variable, update a second vector having the second variable by weighting the first variable with a first coefficient that monotonically increases or monotonically decreases depending on the number of updates, adding the weighted first variable to the corresponding second variable, calculating a problem term using a plurality of the first variables, and adding the problem term to the second variable, and repeat updating of the first vector and the second vector, then initialize the second variable of the second vector using a pseudo random number, and then repeat updating of the first vector and the second vector again.

8. 发明授权

US08395794B2 System for maintaining a cache of printer-readable prioritized content 有权
标题翻译：用于维护打印机可读优先级内容缓存的系统
公开(公告)号：US08395794B2
公开(公告)日：2013-03-12
申请号：US11706698
申请日：2007-02-15
申请人： Robert St. Jacques
发明人： Robert St. Jacques
IPC分类号： G06F7/492 , G06F15/16 , G11C11/06 , G06K15/00
CPC分类号： G06F3/1212 , G06F3/1245 , G06F3/1285
摘要： A system for prioritizing a cache of print jobs associated with at least one print driver includes a workstation having a processing unit and at least one print driver having a processing unit, that interface via a network. The workstation implements a print job request for a document and determines whether a document key identifier associated with the document exists. If not, a key is created. If a printer-readable format for a document associated with the key identifier is stored in or is pre-existing in one of at least two caches, the print driver assigns a prioritization identifier to the format. The system retrieves the printer-readable format from the cache to produce a print job output. Since the cache stores the document in printer-readable format, overall printing time is reduced. The format may be moved from one cache to another depending upon priority. The corresponding method is also disclosed.
摘要翻译：用于对与至少一个打印驱动程序相关联的打印作业的高速缓存进行优先排序的系统包括具有处理单元的工作站和具有经由网络进行接口的处理单元的至少一个打印驱动程序。工作站对文档执行打印作业请求，并确定与文档相关联的文档关键字标识是否存在。如果没有，则创建一个密钥。如果与密钥标识符相关联的文档的打印机可读格式存储在至少两个高速缓存之一中或者已经存在于至少两个高速缓存之一中，则打印驱动程序为该格式分配优先级标识符。系统从高速缓存中检索打印机可读格式以产生打印作业输出。由于缓存以打印机可读格式存储文档，所以整体打印时间减少。取决于优先级，格式可以从一个缓存移动到另一个缓存。还公开了相应的方法。

9. 发明授权

US5506800A Self-checking complementary adder unit 失效
标题翻译：自检互补加法器单元
公开(公告)号：US5506800A
公开(公告)日：1996-04-09
申请号：US215997
申请日：1994-03-22
申请人： Son Dao-Trong
发明人： Son Dao-Trong
IPC分类号： G06F7/499 , G06F7/492 , G06F7/493 , G06F7/50 , G06F7/507 , G06F7/508 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1608 , G06F11/10 , G06F7/507
摘要： A self-checking complementary adder unit used for high performance subtractions comprises two carry select adders (30 and 36) each of which consists of a pair of byte or digit organized ripple carry adders (31, 32 and 37, 38) generating in parallel virtual sums from true and complemented operands based on the assumption that the carry-in signal is 1 or 0. Depending on byte or digit carry signals generated by carry look ahead circuits (33, 39), partial sums are selected from the virtual sums to form a real sum. The outputs of both carry select adders are connected to a multiplexer (42) which is controlled by the high order carry-out signal from one of the carry look ahead circuits representing the sign of a real sum. The multiplexer selects one of the real sums as the result of a subtraction. A sum checker compares cross-wise the parity bits of the virtual sums from both carry select adders and also compares the related carry-out signals from both the ripple carry adders and carry look ahead circuits. The compare results are combined by a logic circuit to generate a result check signal.
摘要翻译：用于高性能减法的自检互补加法器单元包括两个进位选择加法器（30和36），每个进位选择加法器由一对字符或数字组织波纹携带加法器（31,32和37,38）组成，并行虚拟基于进位信号为1或0的假设，从真实和补充的操作数得到的总和。根据由携带前瞻电路（33,39）产生的字节或数字进位信号，从虚拟和中选择部分和一个真正的总和两个进位选择加法器的输出连接到多路复用器（42），该多路复用器（42）由表示真实和的符号的进位查看电路之一的高阶进位输出信号控制。多路复用器选择一个实数和作为减法的结果。和检查器将来自两个进位选择加法器的虚拟和的奇偶校验位进行交叉比较，并且还比较来自波纹携带加法器的相关进位输出信号并携带预先电路。比较结果由逻辑电路组合以产生结果检查信号。

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