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1. 发明授权

US11456747B1 Multiphase frequency to voltage converter 有权
公开(公告)号：US11456747B1
公开(公告)日：2022-09-27
申请号：US17230863
申请日：2021-04-14
申请人： NXP USA, Inc.
发明人： Trevor Mark Newlin
IPC分类号： H03L7/02 , G01R23/06 , H03L7/085 , G01R23/09 , H03L7/097
摘要： A method for multiphase frequency to voltage conversion includes generating for each cycle of an oscillating input, one of a plurality of non-overlapping clocks. A respective voltage in proportion to an input frequency of the oscillating input, is generated in response to each of the non-overlapping clocks, with a respective one of a plurality of frequency to voltage converters. Each of the respective voltages is summated to generate a voltage sum proportional to the input frequency.

2. 发明授权

US11411567B2 Phase interpolation-based fractional-N sampling phase-locked loop 有权
$Phase interpolation-based fractional-N sampling phase-locked loop$
公开(公告)号：US11411567B2
公开(公告)日：2022-08-09
申请号：US17117240
申请日：2020-12-10
申请人： QUALCOMM INCORPORATED
发明人： Masoud Moslehi Bajestan , Giovanni Marucci , Dongmin Park , Marco Zanuso , Yiwu Tang
IPC分类号： H03L7/099 , H03J7/04 , H03L7/02 , H03L7/093 , H03M3/00 , H03K3/037
摘要： A phase-locked loop (PLL) may include a phase-frequency detector (PFD), a phase interpolation (PI)-based sampler, a loop filter, a voltage-controlled oscillator (VCO), and a fractional frequency divider. The PFD output corresponds to a phase error between a reference clock signal and a feedback signal. The PI-based sampler produces a slope signal in response to the PFD output, and adjusts the slope signal in response to a quantization error correction indication. The PI-based sampler also samples the slope signal. The loop filter produces a VCO control signal in response to a sampled slope signal. The VCO control signal controls the VCO frequency. The fractional frequency divider circuit divides the frequency of the VCO output signal and also determines the quantization error correction corresponding to the quantization error introduced by fractional division of the frequency of the VCO output signal.

3. 发明授权

US10008981B2 Integrated clock generator and method therefor 有权
公开(公告)号：US10008981B2
公开(公告)日：2018-06-26
申请号：US15096612
申请日：2016-04-12
申请人： Silicon Laboratories Inc.
发明人： Aaron J. Caffee , Brian G. Drost , Hendricus de Ruijter
IPC分类号： H03B5/08 , H03B5/12 , H03L1/00 , H03B5/36 , H03L1/02 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/22 , H03L7/23 , H03L7/183 , H03L7/197
CPC分类号： H03B5/1234 , H03B5/12 , H03B5/1265 , H03B5/36 , H03L1/00 , H03L1/026 , H03L7/02 , H03L7/087 , H03L7/095 , H03L7/183 , H03L7/1976 , H03L7/22 , H03L7/23
摘要： An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.

4. 发明申请

US20180054204A1 Digitally Reconfigurable Ultra-High Precision Internal Oscillator 审中-公开
公开(公告)号：US20180054204A1
公开(公告)日：2018-02-22
申请号：US15730787
申请日：2017-10-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Abhijit Kumar Das
IPC分类号： H03L7/02 , G06F1/04
CPC分类号： H03L7/02 , G06F1/04
摘要： A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

5. 发明申请

US20170329306A1 CLOSED-LOOP CONTROL DEVICE WITH ADAPTIVE FAULT COMPENSATION 审中-公开
公开(公告)号：US20170329306A1
公开(公告)日：2017-11-16
申请号：US15592933
申请日：2017-05-11
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： MARKUS STEPHAN HASCHKA , PHILIPP ROST , ELMAR SCHÄFERS , TORSTEN SCHÜR , BJÖRN SEELINGER
IPC分类号： G05B19/4063 , G05B19/12 , H03L7/02 , G05B19/408 , G05B19/4099
CPC分类号： G05B19/4063 , G05B5/01 , G05B19/12 , G05B19/4083 , G05B19/4099 , G05B2219/31228 , G05B2219/37493 , G05B2219/45187 , H03L7/02
摘要： A closed-loop control device to control a system to be controlled includes a front node, back node, external tapping point, controller and compensating circuit. The compensating circuit has an inner node, frequency filter, front buffer and back buffer. The front node determines a difference; the back node supplies an external sum signal. A setting device automatically suppresses use of the output signal of the front buffer, supplies the back buffer and the back node with a first excitation signal as the compensation signal and detects a first result signal produced by the first excitation signal. The first result signal is one of the control difference, internal sum signal, output filtered signal of the frequency filter or output signal of the front buffer. The setting device evaluates the first excitation signal and the first result signal, sets a parameter of the frequency filter and the second propagation delay.

6. 发明授权

US09628088B2 Multi-mode crystal oscillators 有权
公开(公告)号：US09628088B2
公开(公告)日：2017-04-18
申请号：US14463658
申请日：2014-08-19
申请人： Texas Instruments Incorporated
发明人： Danielle Griffith , Viral Parikh , Ryan Smith , Per Torstein Roine
IPC分类号： H04B1/40 , H03L7/02
CPC分类号： H03L7/02 , H04B1/40
摘要： Digital control of a crystal oscillator is implemented in a manner that allows frequency accuracy to be traded off dynamically with power consumption. The oscillator transitions between a less accurate/lower power mode and a high accuracy/higher power mode smoothly without requiring any external clock source during the transition. Power consumption is optimized because the crystal oscillator provides the clock source during transitions between the power modes and no other clock source is needed for these transitions. The system can also optimize the startup time and steady state power consumption independently.

7. 发明授权

US09041478B2 Electronic oscillation circuit 有权
标题翻译：电子振荡电路
公开(公告)号：US09041478B2
公开(公告)日：2015-05-26
申请号：US14355081
申请日：2012-09-20
申请人： Anharmonic B.V.
发明人： Antonius Johannes Maria Montagne
IPC分类号： H03B5/32 , H03L7/02 , H03B5/36 , H03B27/00 , H03L1/02
CPC分类号： H03L7/02 , H03B5/36 , H03B27/00 , H03L1/026
摘要： An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal.
摘要翻译：电子振荡器电路具有用于提供第一振荡信号的第一振荡器，用于提供第二振荡信号的第二振荡器，用于输出第一控制信号的第一控制器，作为第一控制器输入和第一振荡信号之间的相位差的函数第一控制器的第二控制器输入; 第二控制器，用于根据第二控制器的第一控制器输入端与第二控制器的第二控制器输入端之间的相位差传递第二控制信号; 谐振器至少第二共振频率，其中第一相移取决于第二激励信号的频率与第二共振频率之间的差异以及处理装置，用于接收第一振荡器信号和第二振荡器信号，确定它们的相互比例，在预先存储的表中查找频率补偿因子并输出补偿的振荡信号。

8. 发明申请

US20150091664A1 CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT 审中-公开
标题翻译：电路设备，振荡器，电子设备和移动对象
公开(公告)号：US20150091664A1
公开(公告)日：2015-04-02
申请号：US14497854
申请日：2014-09-26
申请人： Seiko Epson Corporation
发明人： Hisahiro ITO
IPC分类号： H03L7/02 , H03B5/30
CPC分类号： H03B5/366 , H03J2200/10
摘要： A circuit device includes an oscillation circuit that includes a variable capacitance circuit and performs an operation of oscillating an oscillation element; and a control unit. The variable capacitance circuit includes a plurality of variable capacitance elements. When an operation mode is a first operation mode, the control unit supplies applied voltages in which at least one thereof is a variable voltage to the plurality of variable capacitance elements, and when the operation mode is a second operation mode, the control unit supplies applied voltages which are all fixed voltages to the plurality of variable capacitance elements.
摘要翻译：电路装置包括：振荡电路，包括可变电容电路，并进行摆动振荡元件的动作; 和控制单元。可变电容电路包括多个可变电容元件。当操作模式是第一操作模式时，控制单元将至少其中一个作为可变电压的施加电压提供给多个可变电容元件，并且当操作模式是第二操作模式时，控制单元提供应用对多个可变电容元件都是固定电压的电压。

9. 发明申请

US20130093524A1 DIGITALLY CONTROLLED OSCILLATOR DEVICE AND HIGH FREQUENCY SIGNAL PROCESSING DEVICE 有权
标题翻译：数字控制振荡器装置和高频信号处理装置
公开(公告)号：US20130093524A1
公开(公告)日：2013-04-18
申请号：US13651410
申请日：2012-10-13
申请人： Renesas Mobile Corporation
发明人： Takahiro NAKAMURA
IPC分类号： H03L7/02
CPC分类号： H03L7/02 , H03B5/1206 , H03B5/1265 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03L7/099 , H03L2207/50
摘要： The present invention provides a digitally controlled oscillator device capable of reducing noise away from an oscillation frequency, and a high frequency signal processing device. Fractional capacitances are realized using a plurality of unitary capacitor units, for example. In one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to oscillation output nodes. On the other hand, in the unitary capacitor units other than the one unitary capacitor unit, one ends of two types of capacitive elements are respectively coupled to a fixed voltage. The other ends of one capacitive elements in all the unitary capacitor units are coupled in common, and the other ends of other capacitive elements are also coupled in common. Turning on and off of respective switches in all the unitary capacitor units are controlled in common.
摘要翻译：本发明提供一种能够降低远离振荡频率的噪声的数字控制振荡器装置和高频信号处理装置。例如，使用多个单体电容器单元实现分数电容。在一个单体电容器单元中，两种类型的电容元件的一端分别耦合到振荡输出节点。另一方面，除了一个单一电容器单元之外的单电容器单元中，两种类型的电容元件的一端分别耦合到固定电压。所有单体电容器单元中的一个电容元件的另一端共同耦合，并且其它电容元件的另一端也共同耦合。所有单体电容器单元中的各个开关的导通和关断被共同控制。

10. 发明授权

US08266468B2 Integrated circuit with interpolation to avoid harmonic interference 有权
标题翻译：具有插补的集成电路，避免谐波干扰
公开(公告)号：US08266468B2
公开(公告)日：2012-09-11
申请号：US12899256
申请日：2010-10-06
申请人： Arya Reza Behzad , Mark Gonikberg , Ahmadreza (Reza) Rofougaran
发明人： Arya Reza Behzad , Mark Gonikberg , Ahmadreza (Reza) Rofougaran
IPC分类号： G06F1/00 , G06F1/04 , G06F3/033 , H03L7/02 , H03K3/03 , H03K19/00 , H03K5/01 , H03K9/00 , H04L7/00
CPC分类号： H04B15/02 , H04B15/06 , H04B2215/064 , H04B2215/068 , H04L27/0014 , Y02D70/122 , Y02D70/124
摘要： An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.
摘要翻译：集成电路（IC）包括时钟电路，处理模块和处理电路。时钟电路被耦合以产生数字时钟信号。处理模块被耦合以确定具有标称数字时钟速率的数字时钟信号的谐波分量是否在频带内，并且向时钟电路提供指示以将其速率从标称数字时钟速率调整到调整数字数字时钟信号的谐波分量在频带内的时钟频率。处理电路被耦合以以调整的数字时钟速率处理数据以产生具有对应于标称数字时钟速率的速率的处理数据，并且以插值速率内插处理后的数据，以产生经内插处理的数据，该数据具有速率对应于插补率。

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