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1. 发明授权

US07541297B2 Method and system for improving dielectric film quality for void free gap fill 有权
标题翻译：改善空隙填隙电介质膜质量的方法和系统
公开(公告)号：US07541297B2
公开(公告)日：2009-06-02
申请号：US11876541
申请日：2007-10-22
申请人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
发明人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L21/31612 , C23C16/045 , C23C16/24 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/76837
摘要： A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.
摘要翻译：在基板上形成氧化硅层的方法。该方法包括提供衬底并形成覆盖衬底的至少一部分的第一氧化硅层，第一氧化硅层包括残留的水，羟基和碳类。该方法还包括将第一氧化硅层暴露于多个含硅物质以形成与第一氧化硅层部分混合的多个非晶硅组分。此外，该方法包括在氧化环境中将与多个非晶硅组分部分混合的第一氧化硅层退火以在衬底上形成第二氧化硅层。至少一部分非晶硅组分被氧化成第二氧化硅层的一部分，并且基本上去除了第二氧化硅层中未反应的残余羟基和碳物质。

2. 发明申请

US20090104789A1 METHOD AND SYSTEM FOR IMPROVING DIELECTRIC FILM QUALITY FOR VOID FREE GAP FILL 有权
标题翻译：用于改善无电隙隙填料的电介质膜质量的方法和系统
公开(公告)号：US20090104789A1
公开(公告)日：2009-04-23
申请号：US11876541
申请日：2007-10-22
申请人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
发明人： Abhijit Basu Mallick , Jeffrey C. Munro , Linlin Wang , Srinivas D. Nemani , Yi Zheng , Zheng Yuan , Dimitry Lubomirsky , Ellie Y. Yieh
IPC分类号： H01L21/31
CPC分类号： H01L21/31612 , C23C16/045 , C23C16/24 , C23C16/401 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02274 , H01L21/0228 , H01L21/02337 , H01L21/0234 , H01L21/76837
摘要： A method of forming a silicon oxide layer on a substrate. The method includes providing a substrate and forming a first silicon oxide layer overlying at least a portion of the substrate, the first silicon oxide layer including residual water, hydroxyl groups, and carbon species. The method further includes exposing the first silicon oxide layer to a plurality of silicon-containing species to form a plurality of amorphous silicon components being partially intermixed with the first silicon oxide layer. Additionally, the method includes annealing the first silicon oxide layer partially intermixed with the plurality of amorphous silicon components in an oxidative environment to form a second silicon oxide layer on the substrate. At least a portion of amorphous silicon components are oxidized to become part of the second silicon oxide layer and unreacted residual hydroxyl groups and carbon species in the second silicon oxide layer are substantially removed.
摘要翻译：在基板上形成氧化硅层的方法。该方法包括提供衬底并形成覆盖衬底的至少一部分的第一氧化硅层，第一氧化硅层包括残留的水，羟基和碳类。该方法还包括将第一氧化硅层暴露于多个含硅物质以形成与第一氧化硅层部分混合的多个非晶硅组分。此外，该方法包括在氧化环境中将与多个非晶硅组分部分混合的第一氧化硅层退火以在衬底上形成第二氧化硅层。至少一部分非晶硅组分被氧化成第二氧化硅层的一部分，并且基本上去除了第二氧化硅层中未反应的残余羟基和碳物质。

3. 发明授权

US07033945B2 Gap filling with a composite layer 失效
标题翻译：间隙填充复合层
公开(公告)号：US07033945B2
公开(公告)日：2006-04-25
申请号：US10857829
申请日：2004-06-01
申请人： Jeong Soo Byun , Zheng Yuan , Shankar Venkataraman , M. Ziaul Karim , Thanh N. Pham , Ellie Y. Yieh
发明人： Jeong Soo Byun , Zheng Yuan , Shankar Venkataraman , M. Ziaul Karim , Thanh N. Pham , Ellie Y. Yieh
IPC分类号： H01L21/311
CPC分类号： H01L21/76224
摘要： A method of filling a gap formed between adjacent raised surfaces on a substrate. In one embodiment the method comprises depositing a boron-doped silica glass (BSG) layer over the substrate to partially fill the gap using a thermal CVD process; exposing the BSG layer to a steam ambient at a temperature above the BSG layer's Eutectic temperature; removing an upper portion of the BSG layer by exposing the layer to a fluorine-containing etchant; and depositing an undoped silica glass (USG) layer over the BSG layer to fill the remainder of the gap.
摘要翻译：填充在基板上相邻的凸起表面之间形成的间隙的方法。在一个实施例中，该方法包括在衬底上沉积硼掺杂石英玻璃（BSG）层，以使用热CVD工艺部分填充间隙; 在高于BSG层的共晶温度的温度下将BSG层暴露于蒸汽环境; 通过将层暴露于含氟蚀刻剂来除去BSG层的上部; 以及在BSG层上沉积未掺杂的二氧化硅玻璃（USG）层以填补间隙的剩余部分。

4. 发明授权

US07528051B2 Method of inducing stresses in the channel region of a transistor 失效
标题翻译：在晶体管的沟道区域中产生应力的方法
公开(公告)号：US07528051B2
公开(公告)日：2009-05-05
申请号：US10846734
申请日：2004-05-14
申请人： Reza Arghavani , Zheng Yuan , Ellie Y. Yieh , Shankar Venkataraman , Nitin K. Ingle
发明人： Reza Arghavani , Zheng Yuan , Ellie Y. Yieh , Shankar Venkataraman , Nitin K. Ingle
IPC分类号： H01L21/76
CPC分类号： H01L29/6656 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A method of fabricating a semiconductor device, where the method includes forming a transistor on a substrate, where the transistor includes a channel region configured to conduct charge between a source region and a drain region, forming a trench adjacent to the transistor, depositing a material on the substrate and within the trench, and annealing the material, where the material is tensile following the annealing and creates a tensile stress in the channel region. Also, a method of forming a trench isolation in a semiconductor device, where the method includes forming a trench in a substrate, forming a material within the trench at a lower deposition rate, forming the material on the substrate at a higher deposition rate after the depositing of the material within the trench, and annealing the material, where after the annealing the material in the trench is tensile.
摘要翻译：一种制造半导体器件的方法，其中所述方法包括在衬底上形成晶体管，其中所述晶体管包括被配置为在源极区域和漏极区域之间传导电荷的沟道区域，形成与所述晶体管相邻的沟槽，在衬底上和沟槽内，并对材料进行退火，其中材料在退火之后是拉伸的，并且在沟道区域中产生拉伸应力。另外，在半导体器件中形成沟槽隔离的方法，其中所述方法包括在衬底中形成沟槽，以较低的沉积速率在沟槽内形成材料，在衬底上以更高的沉积速率在衬底上形成材料在沟槽内沉积材料并退火材料，其中在退火之后，沟槽中的材料是拉伸的。

5. 发明申请

US20090031955A1 VACUUM CHUCKING HEATER OF AXISYMMETRICAL AND UNIFORM THERMAL PROFILE 审中-公开
标题翻译：轴对称和均匀热轮廓的真空开关加热器
公开(公告)号：US20090031955A1
公开(公告)日：2009-02-05
申请号：US11830589
申请日：2007-07-30
申请人： Siqing Lu , Balaji Chandrasekaran , Paul Edward Gee , Nitin K. Ingle , Dmitry Lubomirsky , Zheng Yuan , Ellie Y. Yieh
发明人： Siqing Lu , Balaji Chandrasekaran , Paul Edward Gee , Nitin K. Ingle , Dmitry Lubomirsky , Zheng Yuan , Ellie Y. Yieh
IPC分类号： C23C16/00 , B23B31/30
CPC分类号： C23C16/4586 , C23C16/4584 , Y10T279/11
摘要： Embodiments of a vacuum chuck having an axisymmetrical and/or more uniform thermal profile are provided herein. In some embodiments, a vacuum chuck includes a body having a support surface for supporting a substrate thereupon; a plurality of axisymmetrically arranged grooves formed in the support surface, at least some of the grooves intersecting; and a plurality of chucking holes formed through the body and within the grooves, the chucking holes for fluidly coupling the grooves to a vacuum source during operation, wherein the chucking holes are disposed in non-intersecting portions of the grooves.
摘要翻译：具有轴对称和/或更均匀的热分布的真空吸盘的实施例在此提供。在一些实施例中，真空卡盘包括具有用于支撑基板的支撑表面的主体; 形成在支撑表面中的多个轴对称布置的槽，至少一些槽相交; 以及在所述槽内形成的多个夹持孔，所述夹持孔用于在操作期间将所述槽流体耦合到真空源，其中所述夹紧孔设置在所述槽的非交叉部分中。

6. 发明授权

US07087497B2 Low-thermal-budget gapfill process 有权
标题翻译：低热量预算的填隙过程
公开(公告)号：US07087497B2
公开(公告)日：2006-08-08
申请号：US10793559
申请日：2004-03-04
申请人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
发明人： Zheng Yuan , Reza Arghavani , Ellie Y Yieh , Shankar Venkataraman
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , C23C16/403 , C23C16/45536 , C23C16/45544 , H01J37/32009 , H01L21/02178 , H01L21/0228 , H01L21/32055 , H01L21/67017 , H01L21/6719 , H01L21/763
摘要： A low-thermal-budget gapfill process is provided for filling a gap formed between two adjacent raised features on a strained-silicon substrate as part of a shallow-trench-isolation process. An electrically insulating liner is deposited using atomic-layer deposition and polysilicon is deposited over the electrically insulating liner, with both stages being conducted at temperatures below 700° C.
摘要翻译：提供了一种低热预算的间隙填充方法，用于填充在应变硅衬底上形成的两个相邻隆起特征之间的间隙，作为浅沟槽隔离工艺的一部分。使用原子层沉积沉积电绝缘衬垫，并且将多晶硅沉积在电绝缘衬垫上，其中两个阶段在低于700℃的温度下进行。

7. 发明申请

US20110114177A1 MIXED SILICON PHASE FILM FOR HIGH EFFICIENCY THIN FILM SILICON SOLAR CELLS 审中-公开
标题翻译：用于高效薄膜硅太阳能电池的混合硅胶片
公开(公告)号：US20110114177A1
公开(公告)日：2011-05-19
申请号：US12838861
申请日：2010-07-19
申请人： Fan Yang , Lin Zhang , Yi Zheng , Francimar Schmitt , Zheng Yuan
发明人： Fan Yang , Lin Zhang , Yi Zheng , Francimar Schmitt , Zheng Yuan
IPC分类号： H01L31/0264 , H01L31/0376 , H01L31/20
CPC分类号： H01L31/03685 , H01L31/03762 , H01L31/075 , H01L31/076 , H01L31/1824 , H01L31/202 , Y02E10/545 , Y02E10/548 , Y02P70/521
摘要： A method and apparatus for forming solar cells is provided. In one embodiment, a photovoltaic device includes a first p-i-n junction cell formed on a substrate, wherein the p-i-n junction cell comprises a p-type silicon containing layer, an intrinsic type silicon containing layer formed over the p-type silicon containing layer, and a n-type silicon containing layer formed over the intrinsic type silicon containing layer, wherein the intrinsic type silicon containing layer comprises a first pair of microcrystalline layer and amorphous silicon layer.
摘要翻译：提供一种用于形成太阳能电池的方法和装置。在一个实施例中，光伏器件包括形成在衬底上的第一pin结单元，其中该pin结单元包括p型含硅层，在p型含硅层上形成本征型含硅层，以及在本征型含硅层上形成n型含硅层，其中本征型含硅层包括第一对微晶层和非晶硅层。

8. 发明授权

US07939422B2 Methods of thin film process 有权
标题翻译：薄膜工艺方法
公开(公告)号：US07939422B2
公开(公告)日：2011-05-10
申请号：US11947674
申请日：2007-11-29
申请人： Nitin K. Ingle , Jing Tang , Yi Zheng , Zheng Yuan , Zhenbin Ge , Xinliang Lu , Chien-Teh Kao , Vikash Banthia , William H. McClintock , Mei Chang
发明人： Nitin K. Ingle , Jing Tang , Yi Zheng , Zheng Yuan , Zhenbin Ge , Xinliang Lu , Chien-Teh Kao , Vikash Banthia , William H. McClintock , Mei Chang
IPC分类号： H01L21/76
CPC分类号： H01L21/67253 , H01L21/02164 , H01L21/0217 , H01L21/3105 , H01L21/31116 , H01L21/76232
摘要： A method for forming a semiconductor structure includes forming a plurality of features across a surface of a substrate, with at least one space being between two adjacent features. A first dielectric layer is formed on the features and within the at least one space. A portion of the first dielectric layer interacts with a reactant derived from a first precursor and a second precursor to form a first solid product. The first solid product is decomposed to substantially remove the portion of the first dielectric layer. A second dielectric layer is formed to substantially fill the at least one space.
摘要翻译：一种用于形成半导体结构的方法包括跨越衬底的表面形成多个特征，其中至少一个空间位于两个相邻特征之间。第一电介质层形成在特征上并且在至少一个空间内。第一介电层的一部分与衍生自第一前体和第二前体的反应物相互作用以形成第一固体产物。第一固体产物被分解以基本上除去第一介电层的部分。形成第二电介质层以基本上填充至少一个空间。

9. 发明申请

US20120171852A1 REMOTE HYDROGEN PLASMA SOURCE OF SILICON CONTAINING FILM DEPOSITION 审中-公开
标题翻译：含有薄膜沉积的硅离子等离子体源
公开(公告)号：US20120171852A1
公开(公告)日：2012-07-05
申请号：US13266978
申请日：2010-08-02
申请人： Zheng Yuan , Mandar B. Pandit , Francimar C. Schmitt , Yi Zheng , Fan Yang , Lipan Li , Alan Tso , Dustin W. Ho , Tom K. Cho , Randhir Thakur
发明人： Zheng Yuan , Mandar B. Pandit , Francimar C. Schmitt , Yi Zheng , Fan Yang , Lipan Li , Alan Tso , Dustin W. Ho , Tom K. Cho , Randhir Thakur
IPC分类号： H01L21/20 , C23C16/50
CPC分类号： H01L21/02532 , C23C16/24 , C23C16/452 , C23C16/505 , H01J37/32357 , H01J37/32449 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L31/076 , H01L31/1804 , H01L31/1824 , H01L31/202 , Y02E10/545 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： Methods for forming and treating a silicon containing layer in a thin film transistor structure or solar cell devices are provided. In one embodiment, a method for forming a silicon containing layer on a substrate includes providing a substrate into a processing chamber, providing a gas mixture having a silicon containing gas into the processing chamber, providing a hydrogen containing gas from a remote plasma source coupled to the processing chamber, applying a RF power less than 17.5 mWatt/cm2 to the processing chamber, and forming a silicon containing layer on the substrate.
摘要翻译：提供了在薄膜晶体管结构或太阳能电池器件中形成和处理含硅层的方法。在一个实施例中，在衬底上形成含硅层的方法包括将衬底提供到处理室中，将具有含硅气体的气体混合物提供到处理室中，从远程等离子体源提供含氢气体，其耦合到处理室，向处理室施加小于17.5mW / cm 2的RF功率，并在基板上形成含硅层。

10. 发明申请

US20110275200A1 METHODS OF DYNAMICALLY CONTROLLING FILM MICROSTRUCTURE FORMED IN A MICROCRYSTALLINE LAYER 审中-公开
标题翻译：在微晶层中形成薄膜微结构的动态控制方法
公开(公告)号：US20110275200A1
公开(公告)日：2011-11-10
申请号：US13098072
申请日：2011-04-29
申请人： Yi Zheng , Guangchi Xuan , Zheng Yuan , Brian Shieh
发明人： Yi Zheng , Guangchi Xuan , Zheng Yuan , Brian Shieh
IPC分类号： H01L21/205
CPC分类号： C23C16/24 , C23C16/0272 , C23C16/505 , C23C16/52 , C30B25/105 , C30B29/06 , H01L31/076 , H01L31/1824 , Y02E10/545 , Y02E10/548 , Y02P70/521
摘要： A method for an intrinsic type microcrystalline silicon layer is provided. In one embodiment, a method for forming an intrinsic type microcrystalline silicon layer includes dynamically ramping up a silane gas supplied in a gas mixture to a surface of a substrate disposed in a processing chamber, dynamically ramping down a RF power applied in the gas mixture supplied to the processing chamber to form a plasma in the gas mixture, and forming an intrinsic type microcrystalline silicon layer on the substrate.
摘要翻译：提供本征型微晶硅层的方法。在一个实施方案中，用于形成本征型微晶硅层的方法包括将在气体混合物中供应的硅烷气体动态地升高到设置在处理室中的基板的表面，动态地降低施加在所提供的气体混合物中的RF功率到处理室中以在气体混合物中形成等离子体，并在衬底上形成本征型微晶硅层。

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