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1. 发明申请

US20140317337A1 METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH (PCMS) 审中-公开
标题翻译：元数据管理和支持相位变化记忆与开关（PCMS）
公开(公告)号：US20140317337A1
公开(公告)日：2014-10-23
申请号：US13997215
申请日：2011-12-30
申请人： Leena K. Puthiyedath , Marc T. Jones , R. Scott Tetrick , Robert J. Royer, Jr. , Raj K. Ramanujan , Glenn J. Hinton , Blaise Fanning , Robert S. Gittins , Mark A. Schmisseur , Frank T. Hady , Robert W. Faber
发明人： Leena K. Puthiyedath , Marc T. Jones , R. Scott Tetrick , Robert J. Royer, Jr. , Raj K. Ramanujan , Glenn J. Hinton , Blaise Fanning , Robert S. Gittins , Mark A. Schmisseur , Frank T. Hady , Robert W. Faber
IPC分类号： G11C16/34 , G11C14/00 , G06F12/02
CPC分类号： G11C16/3431 , G06F11/1048 , G06F12/0246 , G11C13/0004 , G11C14/0045
摘要： Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与用于PCMS（带有交换机的相变存储器））元件的管理和/或支持相关的方法和装置。在一个实施例中，PCMS控制器允许基于元数据访问PCMS设备。可以使用元数据来提供如本公开中所讨论的效率，耐久性，纠错等。还公开并要求保护其他实施例。

2. 发明申请

US20130268728A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES 有权
标题翻译：用于实现具有不同操作模式的多级记忆层次的装置和方法
公开(公告)号：US20130268728A1
公开(公告)日：2013-10-10
申请号：US13994731
申请日：2011-09-30
申请人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
发明人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0806 , G06F12/0808 , G06F12/0815 , G06F12/0888 , G06F12/0893 , G06F2212/205 , G06F2212/283 , G06F2212/6046 , G06F2212/621 , G06F2212/7201 , G11C7/1045 , G11C7/1072 , G11C13/0004 , G11C14/0045
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。这些更高性能的存储器件被称为“接近存储器”。在一个实施例中，“近存储器”被配置为以多种不同的操作模式操作，包括（但不限于）其中近端存储器作为远存储器的存储器高速缓存操作的第一模式，以及第二模式其中所述近存储器被分配有系统地址空间的第一地址范围，所述远存储器被分配了所述系统地址空间的第二地址范围，其中所述第一范围和第二范围表示整个系统地址空间。

3. 发明授权

US09378142B2 Apparatus and method for implementing a multi-level memory hierarchy having different operating modes 有权
标题翻译：用于实现具有不同操作模式的多级存储器层级的装置和方法
公开(公告)号：US09378142B2
公开(公告)日：2016-06-28
申请号：US13994731
申请日：2011-09-30
申请人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
发明人： Raj K. Ramanujan , Rajat Agarwal , Glenn J. Hinton
IPC分类号： G06F12/00 , G06F12/08 , G06F12/02 , G11C7/10 , G11C13/00
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0806 , G06F12/0808 , G06F12/0815 , G06F12/0888 , G06F12/0893 , G06F2212/205 , G06F2212/283 , G06F2212/6046 , G06F2212/621 , G06F2212/7201 , G11C7/1045 , G11C7/1072 , G11C13/0004 , G11C14/0045
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一层，有时被称为“远存储器”。更高性能的存储器件例如放置在远存储器之前的DRAM，并用于掩盖某些性能限制远记忆这些更高性能的存储器件被称为“近存储器”。在一个实施例中，“近端存储器”被配置为以多种不同的操作模式操作，包括（但不限于）第一模式，其中近端存储器作为远存储器的存储器高速缓冲存储器和第二模式，其中近距离存储器被分配有系统地址空间的第一地址范围，远处存储器被分配系统地址空间的第二地址范围，其中第一范围和第二个范围代表整个系统地址空间。

4. 发明授权

US09600416B2 Apparatus and method for implementing a multi-level memory hierarchy 有权
公开(公告)号：US09600416B2
公开(公告)日：2017-03-21
申请号：US13997189
申请日：2011-09-30
申请人： Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
发明人： Raj K. Ramanujan , Rajat Agarwal , Kai Cheng , Taarinya Polepeddi , Camille C. Raad , David J. Zimmerman , Muthukumar P. Swaminathan , Dimitrios Ziakas , Mohan J. Kumar , Bassam N. Coury , Glenn J. Hinton
IPC分类号： G06F13/12 , G06F13/38 , G06F12/08 , G11C11/406 , G11C14/00
CPC分类号： G06F12/0811 , G06F12/0895 , G06F12/0897 , G06F2212/2024 , G06F2212/205 , G11C11/40615 , G11C14/009 , Y02D10/13
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

5. 发明申请

US20140351660A1 TWO-LEVEL SYSTEM MAIN MEMORY 审中-公开
标题翻译：两级系统主要内存
公开(公告)号：US20140351660A1
公开(公告)日：2014-11-27
申请号：US14105708
申请日：2013-12-13
申请人： Eric J. DAHLEN , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. DAHLEN , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G11C14/00 , G06F11/07 , G06F12/02
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

6. 发明申请

US20140006848A1 BAD BLOCK MANAGEMENT MECHANISM 有权
标题翻译：边框管理机制
公开(公告)号：US20140006848A1
公开(公告)日：2014-01-02
申请号：US13537969
申请日：2012-06-29
申请人： RAJ K. RAMANUJAN , Glenn J. Hinton , David J. Zimmerman
发明人： RAJ K. RAMANUJAN , Glenn J. Hinton , David J. Zimmerman
IPC分类号： G11B20/18
CPC分类号： G11B20/1883 , G11C29/82 , G11C29/886
摘要： A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.
摘要翻译：一种系统包括非易失性随机存取存储器（NVRAM）装置和控制器逻辑，用于检测装置内的坏块，通过将坏块的地址分配给替换来退出坏块并用替换块替换坏块块。

7. 发明授权

US09418700B2 Bad block management mechanism 有权
标题翻译：坏块管理机制
公开(公告)号：US09418700B2
公开(公告)日：2016-08-16
申请号：US13537969
申请日：2012-06-29
申请人： Raj K. Ramanujan , Glenn J. Hinton , David J. Zimmerman
发明人： Raj K. Ramanujan , Glenn J. Hinton , David J. Zimmerman
IPC分类号： G11C29/00 , G11B20/18
CPC分类号： G11B20/1883 , G11C29/82 , G11C29/886
摘要： A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.
摘要翻译：一种系统包括非易失性随机存取存储器（NVRAM）装置和控制器逻辑，用于检测装置内的坏块，通过将坏块的地址分配给替换来退出坏块并用替换块替换坏块块。

8. 发明授权

US08612676B2 Two-level system main memory 有权
标题翻译：二级系统主存
公开(公告)号：US08612676B2
公开(公告)日：2013-12-17
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

9. 发明申请

US20120166891A1 TWO-LEVEL SYSTEM MAIN MEMORY 有权
标题翻译：两级系统主要内存
公开(公告)号：US20120166891A1
公开(公告)日：2012-06-28
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

10. 发明申请

US20100250834A1 METHOD AND SYSTEM TO PERFORM CACHING BASED ON FILE-LEVEL HEURISTICS 有权
标题翻译：基于文件级别进行缓存的方法和系统
公开(公告)号：US20100250834A1
公开(公告)日：2010-09-30
申请号：US12415595
申请日：2009-03-31
申请人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
发明人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
IPC分类号： G06F12/00 , G06F12/08 , G06F12/02
CPC分类号： G06F12/0862 , G06F12/0866 , G06F12/0888 , G06F12/121 , G06F2212/222 , G06F2212/6028
摘要： A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.
摘要翻译：至少基于一个或多个文件级启发式方法和系统执行缓存。缓存设备中的存储介质的缓存由高速缓存策略引擎执行。高速缓存策略引擎接收存储介质的数据的输入/输出访问的文件级信息，并基于接收到的文件级信息来高速缓存或者将高速缓存设备中的存储介质的数据移出。通过利用关于与存储介质的磁盘扇区或逻辑块地址相关联的文件和文件操作的信息，高速缓存策略引擎可以更好地决定要缓存到缓存设备或从高速缓存设备移出的存储介质的数据选择在本发明的一个实施例中。可以实现更高的缓存命中率，并提高利用缓存策略引擎的系统的性能。

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