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1. 发明申请

US20140317337A1 METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH (PCMS) 审中-公开
标题翻译：元数据管理和支持相位变化记忆与开关（PCMS）
公开(公告)号：US20140317337A1
公开(公告)日：2014-10-23
申请号：US13997215
申请日：2011-12-30
申请人： Leena K. Puthiyedath , Marc T. Jones , R. Scott Tetrick , Robert J. Royer, Jr. , Raj K. Ramanujan , Glenn J. Hinton , Blaise Fanning , Robert S. Gittins , Mark A. Schmisseur , Frank T. Hady , Robert W. Faber
发明人： Leena K. Puthiyedath , Marc T. Jones , R. Scott Tetrick , Robert J. Royer, Jr. , Raj K. Ramanujan , Glenn J. Hinton , Blaise Fanning , Robert S. Gittins , Mark A. Schmisseur , Frank T. Hady , Robert W. Faber
IPC分类号： G11C16/34 , G11C14/00 , G06F12/02
CPC分类号： G11C16/3431 , G06F11/1048 , G06F12/0246 , G11C13/0004 , G11C14/0045
摘要： Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与用于PCMS（带有交换机的相变存储器））元件的管理和/或支持相关的方法和装置。在一个实施例中，PCMS控制器允许基于元数据访问PCMS设备。可以使用元数据来提供如本公开中所讨论的效率，耐久性，纠错等。还公开并要求保护其他实施例。

2. 发明申请

US20130283079A1 METHOD AND SYSTEM FOR PROVIDING INSTANT RESPONSES TO SLEEP STATE TRANSITIONS WITH NON-VOLATILE RANDOM ACCESS MEMORY 有权
标题翻译：用非易失性随机存取存储器向休眠状态转换提供即时响应的方法和系统
公开(公告)号：US20130283079A1
公开(公告)日：2013-10-24
申请号：US13976903
申请日：2011-12-13
申请人： Leena K. Puthiyedath , Raj K. Ramanujan , Michael Rothman , Blaise Fanning , Vincent J. Zimmer
发明人： Leena K. Puthiyedath , Raj K. Ramanujan , Michael Rothman , Blaise Fanning , Vincent J. Zimmer
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.
摘要翻译：在计算机系统中使用非易失性随机存取存储器（NVRAM）来为睡眠状态转换提供即时响应。计算机系统包括耦合到NVRAM的处理器，其可由处理器访问而不经过I / O子系统。 NVRAM是字节可重写的，可由处理器字节擦除。响应于进入供电的睡眠状态的请求，计算机系统将动态睡眠状态转换为关闭休眠状态，并将系统存储器上下文存储在NVRAM中。动力睡眠状态被定义为向计算机系统中的易失性随机存取存储器提供电力的状态，并且断电睡眠状态被定义为从易失性随机存取存储器去除电力的状态。响应于唤醒事件，计算机系统使用存储在NVRAM中的系统存储器上下文来恢复工作状态操作。

3. 发明授权

US09958926B2 Method and system for providing instant responses to sleep state transitions with non-volatile random access memory 有权
公开(公告)号：US09958926B2
公开(公告)日：2018-05-01
申请号：US13976903
申请日：2011-12-13
申请人： Leena K. Puthiyedath , Raj K. Ramanujan , Michael Rothman , Blaise Fanning , Vincent J. Zimmer
发明人： Leena K. Puthiyedath , Raj K. Ramanujan , Michael Rothman , Blaise Fanning , Vincent J. Zimmer
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

4. 发明授权

US09229853B2 Method and system for data de-duplication 有权
标题翻译：重复数据删除的方法和系统
公开(公告)号：US09229853B2
公开(公告)日：2016-01-05
申请号：US13977069
申请日：2011-12-20
申请人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
发明人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
IPC分类号： G06F13/12 , G06F7/00 , G06F12/02 , G06F3/06 , G06F12/08
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0641 , G06F3/0679 , G06F12/0802 , G06F2212/304
摘要： An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed.
摘要翻译：装置可以包括用于存储数据的非易失性随机存取存储器和耦合到非易失性随机存取存储器的处理器。该装置还可以包括数据重复数据删除模块，其可在处理器上操作以读取输入数据的签名，将签名与非易失性随机存取存储器中的第一数据进行比较，并且当签名指示匹配到第一数据。公开和要求保护其他实施例。

5. 发明申请

US20130318288A1 METHOD AND SYSTEM FOR DATA DE-DUPLICATION 有权
标题翻译：用于数据失真的方法和系统
公开(公告)号：US20130318288A1
公开(公告)日：2013-11-28
申请号：US13977069
申请日：2011-12-20
申请人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
发明人： Jawad B. Khan , Ningde Xie , Raj K. Ramanujan , Leena K. Puthiyedath
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0641 , G06F3/0679 , G06F12/0802 , G06F2212/304
摘要： An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed.
摘要翻译：装置可以包括用于存储数据的非易失性随机存取存储器和耦合到非易失性随机存取存储器的处理器。该装置还可以包括数据重复数据删除模块，其可在处理器上操作以读取输入数据的签名，将签名与非易失性随机存取存储器中的第一数据进行比较，并且当签名指示匹配第一个数据。公开和要求保护其他实施例。

6. 发明申请

US20140006696A1 APPARATUS AND METHOD FOR PHASE CHANGE MEMORY DRIFT MANAGEMENT 有权
标题翻译：相位变化管理的设备和方法
公开(公告)号：US20140006696A1
公开(公告)日：2014-01-02
申请号：US13994116
申请日：2011-12-20
申请人： Raj K. Ramanujan , Mark A. Schmisseur
发明人： Raj K. Ramanujan , Mark A. Schmisseur
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C2013/0054 , G11C2013/0057
摘要： A system and method are described for selecting a demarcation voltage for read and write operations. Embodiments of the invention provide a scheme to use multiple VDMs to cover the case where power-on drift is different from power-off drift of the PCMS cells. The controller automatically manages this through tracking refreshes and writes. In addition, the embodiments of the invention provide an efficient scheme to reduce the performance impact of the penalty box following a write by tracking recent write addresses through a hash-table or similar scheme. By way of example, a method in accordance with one embodiment comprises: detecting a read operation directed to a first block of a PCMS memory; determining whether a write operation has previously occurred to the first block within a specified amount of time prior to the read operation; using a first demarcation voltage (VDM) for the read operation if the write operation has previously occurred to the first block within the specified amount of time prior to the write operation; and using a second VDM for the read operation if the write operation has not previously occurred to the first block within the specified amount of time prior to the write or refresh operation.
摘要翻译：描述了用于选择用于读取和写入操作的分界电压的系统和方法。本发明的实施例提供了使用多个VDM来覆盖上电漂移与PCMS单元的断电漂移不同的情况的方案。控制器通过跟踪刷新和写入自动进行管理。此外，本发明的实施例提供了一种有效的方案，以通过通过散列表或类似方案跟踪最近的写入地址来减少写入之后的惩罚盒的性能影响。作为示例，根据一个实施例的方法包括：检测针对PCMS存储器的第一块的读取操作; 在所述读取操作之前的指定时间内确定是否先前对所述第一块发生了写入操作; 如果在写操作之前的指定时间内先前已经对第一块发生写操作，则使用第一分界电压（VDM）作为读操作; 以及如果在所述写入或刷新操作之前的所述指定时间量内的所述第一块以前没有发生写入操作，则使用第二VDM进行所述读取操作。

7. 发明申请

US20180089098A1 LOCAL AND REMOTE DUAL ADDRESS DECODING 审中-公开
公开(公告)号：US20180089098A1
公开(公告)日：2018-03-29
申请号：US15279319
申请日：2016-09-28
申请人： Francesc Cesc Guim Bernat , Kshitij A. Doshi , Steen Larsen , Mark A. Schmisseur , Raj K. Ramanujan
发明人： Francesc Cesc Guim Bernat , Kshitij A. Doshi , Steen Larsen , Mark A. Schmisseur , Raj K. Ramanujan
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/0813 , G06F12/1441 , G06F21/00 , G06F2212/1041 , G06F2212/657
摘要： Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.

8. 发明授权

US09286205B2 Apparatus and method for phase change memory drift management 有权
标题翻译：相变记忆漂移管理的装置和方法
公开(公告)号：US09286205B2
公开(公告)日：2016-03-15
申请号：US13994116
申请日：2011-12-20
申请人： Raj K. Ramanujan , Mark A. Schmisseur
发明人： Raj K. Ramanujan , Mark A. Schmisseur
IPC分类号： G06F13/00 , G06F12/02 , G06F12/08 , G11C13/00 , G11C16/34
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/214 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C2013/0054 , G11C2013/0057
摘要： A system and method are described for selecting a demarcation voltage for read and write operations. Embodiments of the invention provide a scheme to use multiple VDMs to cover the case where power-on drift is different from power-off drift of the PCMS cells. The controller automatically manages this through tracking refreshes and writes. In addition, the embodiments of the invention provide an efficient scheme to reduce the performance impact of the penalty box following a write by tracking recent write addresses through a hash-table or similar scheme. By way of example, a method in accordance with one embodiment comprises: detecting a read operation directed to a first block of a PCMS memory; determining whether a write operation has previously occurred to the first block within a specified amount of time prior to the read operation; using a first demarcation voltage (VDM) for the read operation if the write operation has previously occurred to the first block within the specified amount of time prior to the write operation; and using a second VDM for the read operation if the write operation has not previously occurred to the first block within the specified amount of time prior to the write or refresh operation.
摘要翻译：描述了用于选择用于读取和写入操作的分界电压的系统和方法。本发明的实施例提供了使用多个VDM来覆盖上电漂移与PCMS单元的断电漂移不同的情况的方案。控制器通过跟踪刷新和写入自动进行管理。此外，本发明的实施例提供了一种有效的方案，以通过通过散列表或类似方案跟踪最近的写入地址来减少写入之后的惩罚盒的性能影响。作为示例，根据一个实施例的方法包括：检测针对PCMS存储器的第一块的读取操作; 在所述读取操作之前的指定时间内确定是否先前对所述第一块发生了写入操作; 如果在写操作之前的指定时间内先前已经对第一块发生写操作，则使用第一分界电压（VDM）作为读操作; 以及如果在所述写入或刷新操作之前的所述指定时间量内的所述第一块以前没有发生写入操作，则使用第二VDM进行所述读取操作。

9. 发明授权

US09418700B2 Bad block management mechanism 有权
标题翻译：坏块管理机制
公开(公告)号：US09418700B2
公开(公告)日：2016-08-16
申请号：US13537969
申请日：2012-06-29
申请人： Raj K. Ramanujan , Glenn J. Hinton , David J. Zimmerman
发明人： Raj K. Ramanujan , Glenn J. Hinton , David J. Zimmerman
IPC分类号： G11C29/00 , G11B20/18
CPC分类号： G11B20/1883 , G11C29/82 , G11C29/886
摘要： A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and replaces the bad block with a replacement block by assigning the address of the bad block to the replacement block.
摘要翻译：一种系统包括非易失性随机存取存储器（NVRAM）装置和控制器逻辑，用于检测装置内的坏块，通过将坏块的地址分配给替换来退出坏块并用替换块替换坏块块。

10. 发明授权

US08612676B2 Two-level system main memory 有权
标题翻译：二级系统主存
公开(公告)号：US08612676B2
公开(公告)日：2013-12-17
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

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