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1. 发明专利

JP2009105829A Traffic shaping apparatus and method 有权
标题翻译：交通形成装置及方法
公开(公告)号：JP2009105829A
公开(公告)日：2009-05-14
申请号：JP2007277842
申请日：2007-10-25
申请人： Nippon Telegr & Teleph Corp , Nippon Telegraph & Telephone East Corp , Nippon Telegraph & Telephone West Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社 , 東日本電信電話株式会社 , 西日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI , YAMAWAKI KOZO , KOYAMA KENICHI , OHATA HIROYOSHI
IPC分类号： H04L12/815 , H04L12/863
摘要： PROBLEM TO BE SOLVED: To perform traffic shaping for controlling a token rate precisely. SOLUTION: By a traffic shaping method, packet transmission is controlled based on a token counter value added by a predetermined period with the token size as an upper limit. When a sum value is added to the token counter value, the token counter value is compared with a value obtained by shifting the token size to the left by a prescribed shift value. When the token counter value is larger than the value obtained by shifting the token size to the left by the shift value, the token size is stored in a token counter storage section as the token counter value. When the transmission request of a packet is received, the transmission of the packet is requested based on the token counter value. When the transmission of the packet is requested, a value obtained by shifting the frame size value of the packet to the left by a shift value is subtracted from the token counter value. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：进行精确控制令牌速率的流量整形。解决方案：通过流量整形方法，基于以令牌大小为上限的预定周期添加的令牌计数器值来控制分组传输。当向令牌计数器值添加和值时，将令牌计数器值与通过将令牌大小向左移动规定的移位值而获得的值进行比较。当令牌计数器值大于通过将令牌大小向左移位移位值而获得的值时，令牌大小作为令牌计数器值存储在令牌计数器存储部分中。当接收到分组的传输请求时，基于令牌计数器值来请求分组的传输。当请求发送分组时，从令牌计数器值中减去通过将分组的帧大小值向左移位移位值而获得的值。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009105669A Method and device for controlling traffic 有权
标题翻译：用于控制交通的方法和装置
公开(公告)号：JP2009105669A
公开(公告)日：2009-05-14
申请号：JP2007275598
申请日：2007-10-23
申请人： Nippon Telegr & Teleph Corp , Nippon Telegraph & Telephone East Corp , Nippon Telegraph & Telephone West Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社 , 東日本電信電話株式会社 , 西日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI , YAMAWAKI KOZO , KOYAMA KENICHI , OHATA HIROYOSHI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/867
摘要： PROBLEM TO BE SOLVED: To provide a high-speed and compact QoS circuit, especially a WFQ circuit for performing queue control. SOLUTION: The WFQ circuit 100 using a weighted round robin has a storage means for storing the values of quotient counters corresponding to each of a plurality of input ports and the value of a remainder counter. The WFQ circuit 100 selects the quotient counter of the minimum value in the quotient counters, transmits a transmission request from an input port corresponding to the selected quotient counter to a later-stage circuit, and updates the values of the quotient counters except the selected one to values obtained by subtracting the values of the selected quotient counter from them. A value obtained by adding the frame length of input from the input port corresponding to the selected quotient counter to the value of the remainder counter corresponding to the input port is divided by the value of a prescribed weight corresponding to the input port. The value of the selected quotient counter is updated by the quotient of a divided result. The value of the remainder counter corresponding to the input port is updated by the remainder. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供高速和紧凑的QoS电路，特别是用于执行队列控制的WFQ电路。解决方案：使用加权轮询的WFQ电路100具有存储装置，用于存储对应于多个输入端口中的每一个的商计数器的值和余数计数器的值。 WFQ电路100选择商计数器中的最小值的商计数器，将对应于所选商计数器的输入端口的发送请求发送到后级电路，并且更新除了选定的一个的商计数器的值通过从它们中减去所选商计数器的值而获得的值。通过将对应于所选商计数器的输入端口输入的帧长度与对应于输入端口的余数计数器的值相加得到的值除以与输入端口对应的规定权重的值。所选商计数器的值由分割结果的商更新。对应于输入端口的余数计数器的值由余数更新。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2011055370A Circuit and method for processing communication 有权
标题翻译：用于处理通信的电路和方法
公开(公告)号：JP2011055370A
公开(公告)日：2011-03-17
申请号：JP2009204064
申请日：2009-09-03
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA TAKAKUNI , KOIKE KEIICHI , OYAMA KATSUICHI
IPC分类号： H04L12/701 , H04L12/70 , H04L12/775
摘要： PROBLEM TO BE SOLVED: To provide a circuit and method for processing communication capable of performing determination of processes adapting to a reception frame in parallel, and suppressing increase of power consumption due to supply of a clock signal. SOLUTION: This circuit for processing communication includes: an analysis section 12 for analyzing a reception frame; search/determination sections 17-1 to 17-N for performing determination of processes adapting to a reception frame in parallel; a clock supply section 14 for supplying a clock signal to the search/determination sections; and a search/determination section selection section 13 for selecting one of the search/determination sections when analysis information is input from the analysis section 12. When one search/determination section 17-i (i is a positive integer satisfying 1≤i≤N) is selected from the search/determination sections, the search/determination section selection section 13 controls the clock supply section 14 to supply the clock signal to the search/determination section 17-i, and controls the clock supply section 14 to stop the supply of the clock signal after the search/determination section 17-i completes search. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于处理能够并行地执行适合于接收帧的处理的确定的通信的电路和方法，并且抑制由于提供时钟信号而造成的功耗的增加。解决方案：用于处理通信的电路包括：用于分析接收帧的分析部分12; 搜索/确定部分17-1至17-N，用于并行地确定适应于接收帧的处理; 时钟提供部分14，用于向搜索/确定部分提供时钟信号; 以及搜索/确定部分选择部分13，用于在从分析部分12输入分析信息时选择搜索/确定部分之一。当一个搜索/确定部分17-i（i是满足1≤i≤N的正整数）从搜索/确定部分中选择时，搜索/确定部分选择部分13控制时钟提供部分14将时钟信号提供给搜索/确定部分17-i，并且控制时钟提供部分14停止供应在搜索/确定部分17-i完成搜索之后的时钟信号。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011004083A Communication quality control device and communication quality control method 有权
标题翻译：通信质量控制设备和通信质量控制方法
公开(公告)号：JP2011004083A
公开(公告)日：2011-01-06
申请号：JP2009144589
申请日：2009-06-17
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/865 , H04L12/867 , H04L29/06
摘要： PROBLEM TO BE SOLVED: To provide a communication quality control device and a communication quality control method capable of reducing a circuit scale and improving the accuracy of scheduling.SOLUTION: In a queue decision part 9, packet information is queued in a specified queue. In a scheduling circuit 10, a comparison value for selecting an input is prepared from a transmission request, a quotient, a round robin value and a value of priority, the input having the smallest comparison value for selecting the input is obtained and a frame length and the transmission request are transmitted to a packet reader 11. In the packet reader 11, a packet is read from a packet buffer 7 according to packet information obtained from the queue 8, and the packet is transmitted to a transmitter 12. In the scheduling circuit 10, a dividend coupling the residual of the input having a minimum value with the frame length of the packet requesting the transmission is divided by the weight of the input, and the quotient and the residual are updated for computing the next comparison value for selecting the input.
摘要翻译：要解决的问题：提供能够减小电路规模并提高调度精度的通信质量控制装置和通信质量控制方法。解决方案：在队列决定部分9中，分组信息在指定队列中排队。在调度电路10中，从发送请求，商，循环值和优先级值准备用于选择输入的比较值，获得用于选择输入的具有最小比较值的输入，并且获得帧长度并且发送请求被发送到分组读取器11.在分组读取器11中，根据从队列8获得的分组信息，从分组缓冲器7读取分组，并将分组发送到发送机12.在调度中电路10，将具有最小值的输入的残差与请求传输的分组的帧长度相除的余数除以输入的权重，并且更新商和残差以计算下一个比较值以进行选择输入。

5. 发明专利

JP2007124118A Communication processing circuit and communication processing method 有权
标题翻译：通信处理电路和通信处理方法
公开(公告)号：JP2007124118A
公开(公告)日：2007-05-17
申请号：JP2005311345
申请日：2005-10-26
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA KOUHO , CHAGI SHUICHI , KOIKE KEIICHI , OYAMA KATSUICHI , HAYASHI TETSUO , NOUCHI HIROYUKI
IPC分类号： H04L12/701 , H04L12/861 , H04L12/931
摘要： PROBLEM TO BE SOLVED: To provide a communication processing circuit capable of transferring a packet which must be transferred to a CPU out of received packets to the CPU without discarding it. SOLUTION: The communication processing circuit is provided with a plurality of queues 73-1 to 73-N. A frame analyzer 31 and a frame search 41 detect frame information of a frame as a target to be input into the CPU from among the frames to be received. A queue input 60 selects the queues 73-1 to 73-N having priorities corresponding to information indicating a factor by which the frame information detected by a detecting means is a target input into the central processing circuit, and generates job information based on this frame information and inputs the generated information into the selected queues 73-1 to 73-N. A queue outputting section 80 orderly reads the job information from the plurality of queues 73-1 to 73-N in conformity with a predetermined queue reading regulation, and inputs the frame information corresponding to the read job information into the CPU. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通信处理电路，其能够将不需要传送到CPU的接收到的分组的分组传送到CPU而不丢弃该通信处理电路。解决方案：通信处理电路设有多个队列73-1至73-N。帧分析器31和帧搜索41从要接收的帧中检测作为要输入到CPU中的目标的帧的帧信息。队列输入60选择具有对应于指示由检测装置检测到的帧信息作为目标输入到中央处理电路的因素的信息的优先级的队列73-1至73-N，并且基于该帧生成作业信息信息并将生成的信息输入到所选择的队列73-1至73-N中。队列输出部分80根据预定的队列读取规则从多个队列73-1至73-N中顺序地读取作业信息，并将与读取的作业信息相对应的帧信息输入到CPU中。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2015056671A 光伝送システムにおける局側装置及び光伝送システム有权
标题翻译：光传输系统和光传输系统中的站台设备
公开(公告)号：JP2015056671A
公开(公告)日：2015-03-23
申请号：JP2013187046
申请日：2013-09-10
申请人：日本電信電話株式会社 , Nippon Telegr & Teleph Corp , Nttエレクトロニクス株式会社 , Ntt Electornics Corp
发明人： KAWAMURA TOMOAKI , TANAKA NOBUYUKI , SHIGEMATSU SATOSHI , KAWAI KENJI , MIURA NAOKI , KARASAWA RYOSUKE , HOSOYA NOBUKO
IPC分类号： H04L12/44 , H04B10/272
摘要：【課題】PONシステム、特に10G−EPONシステムにおけるONU1台あたりのシステムコストをできるだけ小さくする。【解決手段】OLT1を、N個の光トランシーバ11(11−1〜11−N)と、1個のPON制御回路12と、1つの選択・分配回路13とで構成する。IEEE規格の規定によると、1個の光トランシーバに接続可能なONUの台数は最大で32台であるので、N個の光トランシーバ11と1個のPON制御回路12と1つの選択・分配回路13との構成により、OLT1にN?32台のONUを収容させることが可能となる。例えば、光トランシーバ11を4個使用すると、OLT1には4?32=128台のONUを収容させることが可能となる。これにより、ONU1台あたりのシステムコストが小さくなる。【選択図】図1
摘要翻译：要解决的问题：在PON系统，特别是10G-EPON系统中尽可能多地降低每个ONU的系统成本。解决方案：OLT 1由N个光收发器11（11-1至11-N）组成，一个 PON控制电路12和一个选择/分配电路13.由于根据IEEE标准，可以与一个光收发器连接的ONU的最大数量为32个，所以可以通过N个光收发器11的结构来容纳N×32个ONU ，一个PON控制电路12和一个选择/分配电路13.例如，当使用四个光收发器11时，4×32 = 128个ONU可以容纳在OLT 1中。因此，每个ONU的系统成本降低。

7. 发明专利

JP2011029904A Packet queuing device, and packet queuing method 有权
标题翻译： PACKET QUEUING DEVICE和PACKET QUEUING方法
公开(公告)号：JP2011029904A
公开(公告)日：2011-02-10
申请号：JP2009173257
申请日：2009-07-24
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI
IPC分类号： H04L12/46 , H04L12/70 , H04L12/701 , H04L12/801 , H04L12/861 , H04L12/911
摘要： PROBLEM TO BE SOLVED: To provide a packet queuing device and method enabling high transfer speed, large buffer capacity and not large scale circuit. SOLUTION: The packet queuing device 1 stores a packet to be received by a WAN side receiving section 11 in an external buffer memory 61, and stores a packet to be received by LAN side receiving sections 41-1 to 4 in an internal buffer memory 50. In addition, both packets are controlled by the same QoS control section 31, the packet stored in an external buffer storage section 61 is transmitted from LAN side transmitting sections 56-1 to 4 without being stored in an internal buffer storage section 50. Thus, the packet stored in the external buffer storage section 61 is transferred to the internal buffer storage section 50 while using buffers having transfer rate and buffer capacity according to the receiving sections to prevent generation of packet overflow. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够实现高传输速度，大缓冲器容量和不大规模电路的分组排队装置和方法。解决方案：分组排队装置1将要由WAN侧接收部分11接收的分组存储在外部缓冲存储器61中，并将要由LAN侧接收部分41-1至4接收的分组存储在内部此外，两个分组由相同的QoS控制部分31控制，存储在外部缓冲存储部分61中的分组从LAN侧发送部分56-1至4发送，而不被存储在内部缓冲存储部分因此，存储在外部缓冲存储部分61中的分组被传送到内部缓冲存储部分50，同时使用根据接收部分的具有传输速率和缓冲器容量的缓冲器来防止分组溢出的产生。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2011009876A Buffer circuit and buffer circuit control method 有权
标题翻译：缓冲电路和缓冲电路控制方法
公开(公告)号：JP2011009876A
公开(公告)日：2011-01-13
申请号：JP2009149094
申请日：2009-06-23
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA TAKAKUNI , KOIKE KEIICHI , OYAMA KATSUICHI , HASHIMOTO MASATAKA
IPC分类号： H04L12/931 , H04L12/933
摘要： PROBLEM TO BE SOLVED: To provide a buffer circuit with high efficiency of using a memory for a buffer, and to provide a buffer circuit control method.SOLUTION: The buffer circuit includes: a memory means for the buffer storing frame data; a storage-amount-for-each-attribute-value monitoring means for output of a storage amount for each attribute value indicating the number of the frame data stored in the memory means for the buffer for each attribute of the frame data; a storage decision means for calculating the upper limit amount of the storage amount for each attribute value on the basis of the free capacity of the memory means for the buffer or the storage amount or the increase and decrease, comparing the storage amount for each attribute value with the upper limit amount of the storage amount for each attribute value when the attribute value indicating the attribute of the frame data is input, determining whether to store the frame data of the attribute value in the memory means for the buffer, and for output of information indicating storage presence when storing them; and a memory-for-buffer control means for writing the frame data to the memory means for the buffer when the frame data is input and the information of the storage presence is input from the storage decision means.
摘要翻译：要解决的问题：提供一种使用缓冲器存储器的高效率的缓冲电路，并提供缓冲电路控制方法。解决方案：缓冲电路包括：缓冲器存储帧数据的存储装置; 用于每个属性值监视装置的存储量，用于输出每个属性值的存储量，所述属性值指示存储在所述帧数据的每个属性的所述缓冲器的存储装置中的帧数据的数量; 存储判定装置，用于根据缓冲器的存储装置的可用容量或存储量或增减来计算每个属性值的存储量的上限量，比较每个属性值的存储量当指示了帧数据的属性的属性值被输入时，确定是否将属性值的帧数据存储在缓冲器的存储装置中，并且为了输出指示存储时的存储信息的信息; 以及用于缓冲存储器的控制装置，用于当帧数据被输入并且从存储决定装置输入存储存在的信息时，将帧数据写入缓冲器的存储装置。

9. 发明专利

JP2007166514A Device and method for processing communication 有权
标题翻译：用于处理通信的装置和方法
公开(公告)号：JP2007166514A
公开(公告)日：2007-06-28
申请号：JP2005363511
申请日：2005-12-16
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA KOUHO , KOIKE KEIICHI , OYAMA KATSUICHI , IIZUKA KIMIAKI
IPC分类号： H04L12/701 , H04L12/741 , H04L12/749
摘要： PROBLEM TO BE SOLVED: To provide a communication processing device and a communication processing method that can reduce a circuit by integrating the circuit of a searcher, can utilize a circuit effectively, and can reduce the size of the circuit of the entire searcher. SOLUTION: The communication processing device has a storage that receives a frame, acquires analysis result information containing input interface information or information extracted from the frame, processes or transfers the frame, and stores search condition information for indicating conditions to the analysis result information and determination information for designating the processing or transfer of the frame as an entry of a search table; and the searcher that determines the presence or absence of compatibility with the analysis result information, based on the search condition information of each entry, for outputting determination information on a compatible entry. The storage stores the search category information of each entry, and the search determines the presence or absence of compatibility with the analysis result information according to the search condition information of each entry, and outputs the determination information of the compatible entry as the determination information of the search category of the entry. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供可以通过对搜索器的电路进行积分来减少电路的通信处理装置和通信处理方法，可以有效地利用电路，并且可以减小整个搜索器的电路的尺寸。解决方案：通信处理装置具有接收帧的存储器，获取包含输入接口信息或从帧中提取的信息的分析结果信息，处理或传送帧，并将用于指示条件的搜索条件信息存储到分析结果用于指定作为搜索表的条目的帧的处理或传送的信息和确定信息; 以及基于每个条目的搜索条件信息确定与分析结果信息的兼容性的存在或不存在的搜索器，用于输出关于兼容条目的确定信息。存储器存储每个条目的搜索类别信息，并且搜索根据每个条目的搜索条件信息来确定是否存在与分析结果信息的兼容性，并且输出兼容条目的确定信息作为条目的搜索类别。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007135048A Circuit and method for processing communication 有权
标题翻译：用于处理通信的电路和方法
公开(公告)号：JP2007135048A
公开(公告)日：2007-05-31
申请号：JP2005327263
申请日：2005-11-11
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA KOUHO , CHAGI SHUICHI , KOIKE KEIICHI , OYAMA KATSUICHI , IIZUKA KIMIAKI , TOKORO JUNJI
IPC分类号： H04L12/701 , H04L12/815 , H04L12/931 , H04L13/08
摘要： PROBLEM TO BE SOLVED: To provide a communication processing circuit capable of reading and writing packet data from and to an external storage circuit. SOLUTION: A control unit 17-1 at a memory controller 17 determines whether or not a QoS 70 outputs information containing a transfer destination. When it is determined that the information containing the transfer destination is outputted, the control unit 17-1 reads a frame corresponding to information containing the transfer destination from a DDR-SDRAM3 via a DDR-SDRAMI/F19 for outputting the read frame to a frame generation section 16. When it is determined that the information containing the transfer destination is output, the control unit 17-1 determines whether there is a received frame at a write FIFO 17-3. When it is determined that there is a received frame at a write FIFO 17-3, the control unit 17-1 reads the frame from the write FIFO 17-3 for recording the read frame on the DDR-SDRAM3 via the DDR-SDRAMI/F19. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够从外部存储电路读取和写入分组数据的通信处理电路。解决方案：存储器控制器17处的控制单元17-1确定QoS 70是否输出包含传送目的地的信息。当确定包含传送目的地的信息被输出时，控制单元17-1经由用于将读取的帧输出到帧的DDR-SDRAMI / F19从DDR-SDRAM3读取与包含传送目的地的信息相对应的帧当确定包含传送目的地的信息被输出时，控制单元17-1确定在写入FIFO 17-3是否存在接收帧。当确定在写入FIFO 17-3处存在接收帧时，控制单元17-1从写入FIFO 17-3读取用于通过DDR-SDRAMI / F19。版权所有（C）2007，JPO＆INPIT

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