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1. 发明专利

JP2009105829A Traffic shaping apparatus and method 有权
标题翻译：交通形成装置及方法
公开(公告)号：JP2009105829A
公开(公告)日：2009-05-14
申请号：JP2007277842
申请日：2007-10-25
申请人： Nippon Telegr & Teleph Corp , Nippon Telegraph & Telephone East Corp , Nippon Telegraph & Telephone West Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社 , 東日本電信電話株式会社 , 西日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI , YAMAWAKI KOZO , KOYAMA KENICHI , OHATA HIROYOSHI
IPC分类号： H04L12/815 , H04L12/863
摘要： PROBLEM TO BE SOLVED: To perform traffic shaping for controlling a token rate precisely. SOLUTION: By a traffic shaping method, packet transmission is controlled based on a token counter value added by a predetermined period with the token size as an upper limit. When a sum value is added to the token counter value, the token counter value is compared with a value obtained by shifting the token size to the left by a prescribed shift value. When the token counter value is larger than the value obtained by shifting the token size to the left by the shift value, the token size is stored in a token counter storage section as the token counter value. When the transmission request of a packet is received, the transmission of the packet is requested based on the token counter value. When the transmission of the packet is requested, a value obtained by shifting the frame size value of the packet to the left by a shift value is subtracted from the token counter value. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：进行精确控制令牌速率的流量整形。解决方案：通过流量整形方法，基于以令牌大小为上限的预定周期添加的令牌计数器值来控制分组传输。当向令牌计数器值添加和值时，将令牌计数器值与通过将令牌大小向左移动规定的移位值而获得的值进行比较。当令牌计数器值大于通过将令牌大小向左移位移位值而获得的值时，令牌大小作为令牌计数器值存储在令牌计数器存储部分中。当接收到分组的传输请求时，基于令牌计数器值来请求分组的传输。当请求发送分组时，从令牌计数器值中减去通过将分组的帧大小值向左移位移位值而获得的值。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009105669A Method and device for controlling traffic 有权
标题翻译：用于控制交通的方法和装置
公开(公告)号：JP2009105669A
公开(公告)日：2009-05-14
申请号：JP2007275598
申请日：2007-10-23
申请人： Nippon Telegr & Teleph Corp , Nippon Telegraph & Telephone East Corp , Nippon Telegraph & Telephone West Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社 , 東日本電信電話株式会社 , 西日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI , YAMAWAKI KOZO , KOYAMA KENICHI , OHATA HIROYOSHI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/867
摘要： PROBLEM TO BE SOLVED: To provide a high-speed and compact QoS circuit, especially a WFQ circuit for performing queue control. SOLUTION: The WFQ circuit 100 using a weighted round robin has a storage means for storing the values of quotient counters corresponding to each of a plurality of input ports and the value of a remainder counter. The WFQ circuit 100 selects the quotient counter of the minimum value in the quotient counters, transmits a transmission request from an input port corresponding to the selected quotient counter to a later-stage circuit, and updates the values of the quotient counters except the selected one to values obtained by subtracting the values of the selected quotient counter from them. A value obtained by adding the frame length of input from the input port corresponding to the selected quotient counter to the value of the remainder counter corresponding to the input port is divided by the value of a prescribed weight corresponding to the input port. The value of the selected quotient counter is updated by the quotient of a divided result. The value of the remainder counter corresponding to the input port is updated by the remainder. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供高速和紧凑的QoS电路，特别是用于执行队列控制的WFQ电路。解决方案：使用加权轮询的WFQ电路100具有存储装置，用于存储对应于多个输入端口中的每一个的商计数器的值和余数计数器的值。 WFQ电路100选择商计数器中的最小值的商计数器，将对应于所选商计数器的输入端口的发送请求发送到后级电路，并且更新除了选定的一个的商计数器的值通过从它们中减去所选商计数器的值而获得的值。通过将对应于所选商计数器的输入端口输入的帧长度与对应于输入端口的余数计数器的值相加得到的值除以与输入端口对应的规定权重的值。所选商计数器的值由分割结果的商更新。对应于输入端口的余数计数器的值由余数更新。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2011055370A Circuit and method for processing communication 有权
标题翻译：用于处理通信的电路和方法
公开(公告)号：JP2011055370A
公开(公告)日：2011-03-17
申请号：JP2009204064
申请日：2009-09-03
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA TAKAKUNI , KOIKE KEIICHI , OYAMA KATSUICHI
IPC分类号： H04L12/701 , H04L12/70 , H04L12/775
摘要： PROBLEM TO BE SOLVED: To provide a circuit and method for processing communication capable of performing determination of processes adapting to a reception frame in parallel, and suppressing increase of power consumption due to supply of a clock signal. SOLUTION: This circuit for processing communication includes: an analysis section 12 for analyzing a reception frame; search/determination sections 17-1 to 17-N for performing determination of processes adapting to a reception frame in parallel; a clock supply section 14 for supplying a clock signal to the search/determination sections; and a search/determination section selection section 13 for selecting one of the search/determination sections when analysis information is input from the analysis section 12. When one search/determination section 17-i (i is a positive integer satisfying 1≤i≤N) is selected from the search/determination sections, the search/determination section selection section 13 controls the clock supply section 14 to supply the clock signal to the search/determination section 17-i, and controls the clock supply section 14 to stop the supply of the clock signal after the search/determination section 17-i completes search. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于处理能够并行地执行适合于接收帧的处理的确定的通信的电路和方法，并且抑制由于提供时钟信号而造成的功耗的增加。解决方案：用于处理通信的电路包括：用于分析接收帧的分析部分12; 搜索/确定部分17-1至17-N，用于并行地确定适应于接收帧的处理; 时钟提供部分14，用于向搜索/确定部分提供时钟信号; 以及搜索/确定部分选择部分13，用于在从分析部分12输入分析信息时选择搜索/确定部分之一。当一个搜索/确定部分17-i（i是满足1≤i≤N的正整数）从搜索/确定部分中选择时，搜索/确定部分选择部分13控制时钟提供部分14将时钟信号提供给搜索/确定部分17-i，并且控制时钟提供部分14停止供应在搜索/确定部分17-i完成搜索之后的时钟信号。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011004083A Communication quality control device and communication quality control method 有权
标题翻译：通信质量控制设备和通信质量控制方法
公开(公告)号：JP2011004083A
公开(公告)日：2011-01-06
申请号：JP2009144589
申请日：2009-06-17
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/865 , H04L12/867 , H04L29/06
摘要： PROBLEM TO BE SOLVED: To provide a communication quality control device and a communication quality control method capable of reducing a circuit scale and improving the accuracy of scheduling.SOLUTION: In a queue decision part 9, packet information is queued in a specified queue. In a scheduling circuit 10, a comparison value for selecting an input is prepared from a transmission request, a quotient, a round robin value and a value of priority, the input having the smallest comparison value for selecting the input is obtained and a frame length and the transmission request are transmitted to a packet reader 11. In the packet reader 11, a packet is read from a packet buffer 7 according to packet information obtained from the queue 8, and the packet is transmitted to a transmitter 12. In the scheduling circuit 10, a dividend coupling the residual of the input having a minimum value with the frame length of the packet requesting the transmission is divided by the weight of the input, and the quotient and the residual are updated for computing the next comparison value for selecting the input.
摘要翻译：要解决的问题：提供能够减小电路规模并提高调度精度的通信质量控制装置和通信质量控制方法。解决方案：在队列决定部分9中，分组信息在指定队列中排队。在调度电路10中，从发送请求，商，循环值和优先级值准备用于选择输入的比较值，获得用于选择输入的具有最小比较值的输入，并且获得帧长度并且发送请求被发送到分组读取器11.在分组读取器11中，根据从队列8获得的分组信息，从分组缓冲器7读取分组，并将分组发送到发送机12.在调度中电路10，将具有最小值的输入的残差与请求传输的分组的帧长度相除的余数除以输入的权重，并且更新商和残差以计算下一个比较值以进行选择输入。

5. 发明专利

JP2007124118A Communication processing circuit and communication processing method 有权
标题翻译：通信处理电路和通信处理方法
公开(公告)号：JP2007124118A
公开(公告)日：2007-05-17
申请号：JP2005311345
申请日：2005-10-26
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA KOUHO , CHAGI SHUICHI , KOIKE KEIICHI , OYAMA KATSUICHI , HAYASHI TETSUO , NOUCHI HIROYUKI
IPC分类号： H04L12/701 , H04L12/861 , H04L12/931
摘要： PROBLEM TO BE SOLVED: To provide a communication processing circuit capable of transferring a packet which must be transferred to a CPU out of received packets to the CPU without discarding it. SOLUTION: The communication processing circuit is provided with a plurality of queues 73-1 to 73-N. A frame analyzer 31 and a frame search 41 detect frame information of a frame as a target to be input into the CPU from among the frames to be received. A queue input 60 selects the queues 73-1 to 73-N having priorities corresponding to information indicating a factor by which the frame information detected by a detecting means is a target input into the central processing circuit, and generates job information based on this frame information and inputs the generated information into the selected queues 73-1 to 73-N. A queue outputting section 80 orderly reads the job information from the plurality of queues 73-1 to 73-N in conformity with a predetermined queue reading regulation, and inputs the frame information corresponding to the read job information into the CPU. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通信处理电路，其能够将不需要传送到CPU的接收到的分组的分组传送到CPU而不丢弃该通信处理电路。解决方案：通信处理电路设有多个队列73-1至73-N。帧分析器31和帧搜索41从要接收的帧中检测作为要输入到CPU中的目标的帧的帧信息。队列输入60选择具有对应于指示由检测装置检测到的帧信息作为目标输入到中央处理电路的因素的信息的优先级的队列73-1至73-N，并且基于该帧生成作业信息信息并将生成的信息输入到所选择的队列73-1至73-N中。队列输出部分80根据预定的队列读取规则从多个队列73-1至73-N中顺序地读取作业信息，并将与读取的作业信息相对应的帧信息输入到CPU中。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2007110515A Apparatus and method for controlling packet communication quality 有权
标题翻译：用于控制分组通信质量的装置和方法
公开(公告)号：JP2007110515A
公开(公告)日：2007-04-26
申请号：JP2005300276
申请日：2005-10-14
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA KOUHO , KAWAI KENJI , KOIKE KEIICHI , CHAGI SHUICHI , HAYASHI TETSUO , OYAMA KATSUICHI , NOUCHI HIROYUKI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/865 , H04L12/867 , H04L12/879 , H04L29/06 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To enhance the degree of freedom in adjusting or changing communication quality while realizing high-speed packet processing. SOLUTION: A packet input 1 stores an input packet into a packet buffer 2. A queue controlling unit 5 stores packet information into predetermined queues. A QoS (quality of service) processor 6 receives the packet information from the queues in the decided order in accordance with packet scheduling (priority control, weighting fair control or packet shaping), and notifies a below-described packet transmitter 7 together with a transmission request. The packet transmitter 7 acquires a storing address of a packet to be transmitted in the packet buffer 2 based on the notified packet information or a management number, and transmits the packet to be specified on the basis of the storing address in the packet buffer. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提高在实现高速分组处理的同时调整或改变通信质量的自由度。解决方案：分组输入1将输入分组存储到分组缓冲器2中。队列控制单元5将分组信息存储到预定的队列中。 QoS（服务质量）处理器6根据分组调度（优先级控制，加权公平控制或分组整形）以所确定的顺序从队列中接收分组信息，并且与传输一起通知下述分组发射机7 请求。分组发送器7基于所通知的分组信息或管理编号，获取要在分组缓冲器2中发送的分组的存储地址，并根据该分组缓冲器中的存储地址发送要指定的分组。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2007166279A IPsec CIRCUIT AND IPsec PROCESSING METHOD 有权
标题翻译： IPsec电路和IPsec处理方法
公开(公告)号：JP2007166279A
公开(公告)日：2007-06-28
申请号：JP2005360319
申请日：2005-12-14
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA KOUHO , CHAGI SHUICHI , KOIKE KEIICHI , NOUCHI HIROYUKI , OYAMA KATSUICHI
IPC分类号： H04L9/36 , H04L9/32 , H04L12/70
摘要： PROBLEM TO BE SOLVED: To provide a circuit capable of transmitting and receiving an IPsec packet speedily and inexpensively. SOLUTION: A preprocessor 641 outputs packet data to a cut-type FIFO buffer 642 when the preprocessor determines that a reception packet is the IPsec packet. When an authentication processor 643 receives the input of packet data from the buffer 642, the authentication processor performs authentication by ICV for outputting the packet data to a stored FIFO buffer 644. A decoding processor 646 decodes encrypted data in the packet data outputted from the buffer 644, and rewrites the decoded data for outputting to the stored FIFO buffer 647. A postprocessor 649 generates and outputs data of decapsulated IP packets from the packet data outputted from the buffer 647. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够快速且廉价地发送和接收IPsec分组的电路。解决方案：当预处理器确定接收分组是IPsec分组时，预处理器641将分组数据输出到切割型FIFO缓冲器642。当认证处理器643从缓冲器642接收到分组数据的输入时，认证处理器通过ICV进行认证，以将分组数据输出到存储的FIFO缓冲器644.解码处理器646解码从缓冲器输出的分组数据中的加密数据 644，并且将用于输出的解码数据重写到存储的FIFO缓冲器647.后处理器649从缓冲器647输出的分组数据生成并输出解封装的IP分组的数据。（C）2007，JPO＆INPIT

8. 发明专利

JP2007124117A Communication processing circuit and communication processing method 有权
标题翻译：通信处理电路和通信处理方法
公开(公告)号：JP2007124117A
公开(公告)日：2007-05-17
申请号：JP2005311344
申请日：2005-10-26
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA KOUHO , KOIKE KEIICHI , OYAMA KATSUICHI , HAYASHI TETSUO , ARIMOTO TAKANORI
IPC分类号： H04L12/66 , H04L12/701 , H04L12/741 , H04L12/951
摘要： PROBLEM TO BE SOLVED: To provide a communication processing circuit enabling filter processing and classification processing in each of packets without re-constructing original data, even in the case of a packet subjected to fragment processing. SOLUTION: In the communication processing circuit, when an IP packet to be received is a fragment IP packet and a header, a registration management 55 extracts packet identification information used as common information in the fragment IP packet from a head fragment IP packet, and correlates the extracted packet identification information with processing information to be obtained by classifying the fragment IP packets and records the correlated information as trace searching information in a fragment trace searching table 53. If the IP packet to be received is a fragment IP packet other than the head, a detector 51 extracts the packet identification information from the IP packet, detects processing information corresponding to the extracted packet identification information from the trace searching storage means, and performs processing based on the detected processing information. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：即使在分组处理的分组的情况下，提供一种能够在每个分组中进行滤波处理和分类处理的通信处理电路，而不重新构建原始数据。解决方案：在通信处理电路中，当要接收的IP分组是片段IP分组和报头时，注册管理55从分组IP分组中提取用作分片IP分组中的公共信息的分组标识信息并将所提取的分组识别信息与通过分类分组IP分组获得的处理信息相关联，并将相关信息作为跟踪搜索信息记录在分段跟踪搜索表53中。如果要接收的IP分组是其他分片IP分组检测器51从IP分组中提取分组识别信息，从跟踪搜索存储装置检测与提取的分组识别信息相对应的处理信息，并且基于检测到的处理信息进行处理。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2007110483A Apparatus and method for controlling packet communication quality 有权
公开(公告)号：JP2007110483A
公开(公告)日：2007-04-26
申请号：JP2005299868
申请日：2005-10-14
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA KOUHO , KAWAI KENJI , KOIKE KEIICHI , HAYASHI TETSUO , OYAMA KATSUICHI , NOUCHI HIROYUKI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/865 , H04L12/867 , H04L12/869 , H04L29/06 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To enhance the degree of freedom in adjusting or changing communication quality while realizing high-speed packet processing. SOLUTION: A packet input 1 stores an input packet into a packet buffer 2. A queue controlling unit 5 stores packet information into predetermined queues. A QoS (quality of service) processor 6 receives the packet information from the queues in the decided order in accordance with packet scheduling (priority control, weighting fair control or packet shaping), and notifies a below-described packet transmitter 7 together with a transmission request. The packet transmitter 7 acquires a storing address of a packet to be transmitted in the packet buffer 2 based on the notified packet information or a management number, and transmits the packet to be specified on the basis of the storing address in the packet buffer. COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

JP2007088998A Packet shaping apparatus and method 有权
标题翻译：包装形状装置和方法
公开(公告)号：JP2007088998A
公开(公告)日：2007-04-05
申请号：JP2005277517
申请日：2005-09-26
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA KOUHO , KAWAI KENJI , KOIKE KEIICHI , NOUCHI HIROYUKI , OYAMA KATSUICHI , HAYASHI TETSUO
IPC分类号： H04L12/815 , H04L12/811 , H04L12/819 , H04L12/863 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To provide a packet shaping apparatus in which a circuit scale can be reduced, compared to a conventional apparatus, in a circuit configuration of the packet shaping apparatus for performing packet shaping processing of two models, i.e. a token bucket model and a leaky bucket model. SOLUTION: Token data quantities are successively added to a token bucket resistor by accepting triggers with predetermined intervals. Also, the apparatus includes a selector for selecting a data quantity of a frame size for which a transmission request is made when the processing of the token bucket model is set, and selecting a data quantity of "0" when the processing of the leaky bucket model is set; and a comparator for comparing the data quantity stored in the token bucket register with the data quantity selected by the selector upon receiving the frame transmission request, and outputting a transmission permission of a transmission frame when the data quantity stored in the token bucket register is not less than the data quantity selected by the selector. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种分组整形装置，其中与传统装置相比，可以减少电路规模，在用于执行两个模型的分组整形处理的分组整形装置的电路配置中，即令牌桶型和泄漏桶型。解决方案：通过以预定间隔接受触发，令牌数据量被连续添加到令牌桶式电阻器。此外，该装置包括：选择器，用于在设置令牌桶模型的处理时选择进行发送请求的帧大小的数据量;以及当泄漏桶的处理时选择数据量为“0” 型号设定; 以及比较器，用于将存储在令牌桶寄存器中的数据量与接收到帧发送请求时由选择器选择的数据量进行比较，并且当存储在令牌桶寄存器中的数据量不是时，输出发送帧的发送许可小于选择器选择的数据量。版权所有（C）2007，JPO＆INPIT

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