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1. 发明专利

JP2009105669A Method and device for controlling traffic 有权
标题翻译：用于控制交通的方法和装置
公开(公告)号：JP2009105669A
公开(公告)日：2009-05-14
申请号：JP2007275598
申请日：2007-10-23
申请人： Nippon Telegr & Teleph Corp , Nippon Telegraph & Telephone East Corp , Nippon Telegraph & Telephone West Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社 , 東日本電信電話株式会社 , 西日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI , YAMAWAKI KOZO , KOYAMA KENICHI , OHATA HIROYOSHI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/867
摘要： PROBLEM TO BE SOLVED: To provide a high-speed and compact QoS circuit, especially a WFQ circuit for performing queue control. SOLUTION: The WFQ circuit 100 using a weighted round robin has a storage means for storing the values of quotient counters corresponding to each of a plurality of input ports and the value of a remainder counter. The WFQ circuit 100 selects the quotient counter of the minimum value in the quotient counters, transmits a transmission request from an input port corresponding to the selected quotient counter to a later-stage circuit, and updates the values of the quotient counters except the selected one to values obtained by subtracting the values of the selected quotient counter from them. A value obtained by adding the frame length of input from the input port corresponding to the selected quotient counter to the value of the remainder counter corresponding to the input port is divided by the value of a prescribed weight corresponding to the input port. The value of the selected quotient counter is updated by the quotient of a divided result. The value of the remainder counter corresponding to the input port is updated by the remainder. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供高速和紧凑的QoS电路，特别是用于执行队列控制的WFQ电路。解决方案：使用加权轮询的WFQ电路100具有存储装置，用于存储对应于多个输入端口中的每一个的商计数器的值和余数计数器的值。 WFQ电路100选择商计数器中的最小值的商计数器，将对应于所选商计数器的输入端口的发送请求发送到后级电路，并且更新除了选定的一个的商计数器的值通过从它们中减去所选商计数器的值而获得的值。通过将对应于所选商计数器的输入端口输入的帧长度与对应于输入端口的余数计数器的值相加得到的值除以与输入端口对应的规定权重的值。所选商计数器的值由分割结果的商更新。对应于输入端口的余数计数器的值由余数更新。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009105829A Traffic shaping apparatus and method 有权
标题翻译：交通形成装置及方法
公开(公告)号：JP2009105829A
公开(公告)日：2009-05-14
申请号：JP2007277842
申请日：2007-10-25
申请人： Nippon Telegr & Teleph Corp , Nippon Telegraph & Telephone East Corp , Nippon Telegraph & Telephone West Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社 , 東日本電信電話株式会社 , 西日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI , YAMAWAKI KOZO , KOYAMA KENICHI , OHATA HIROYOSHI
IPC分类号： H04L12/815 , H04L12/863
摘要： PROBLEM TO BE SOLVED: To perform traffic shaping for controlling a token rate precisely. SOLUTION: By a traffic shaping method, packet transmission is controlled based on a token counter value added by a predetermined period with the token size as an upper limit. When a sum value is added to the token counter value, the token counter value is compared with a value obtained by shifting the token size to the left by a prescribed shift value. When the token counter value is larger than the value obtained by shifting the token size to the left by the shift value, the token size is stored in a token counter storage section as the token counter value. When the transmission request of a packet is received, the transmission of the packet is requested based on the token counter value. When the transmission of the packet is requested, a value obtained by shifting the frame size value of the packet to the left by a shift value is subtracted from the token counter value. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：进行精确控制令牌速率的流量整形。解决方案：通过流量整形方法，基于以令牌大小为上限的预定周期添加的令牌计数器值来控制分组传输。当向令牌计数器值添加和值时，将令牌计数器值与通过将令牌大小向左移动规定的移位值而获得的值进行比较。当令牌计数器值大于通过将令牌大小向左移位移位值而获得的值时，令牌大小作为令牌计数器值存储在令牌计数器存储部分中。当接收到分组的传输请求时，基于令牌计数器值来请求分组的传输。当请求发送分组时，从令牌计数器值中减去通过将分组的帧大小值向左移位移位值而获得的值。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2011029904A Packet queuing device, and packet queuing method 有权
标题翻译： PACKET QUEUING DEVICE和PACKET QUEUING方法
公开(公告)号：JP2011029904A
公开(公告)日：2011-02-10
申请号：JP2009173257
申请日：2009-07-24
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI
IPC分类号： H04L12/46 , H04L12/70 , H04L12/701 , H04L12/801 , H04L12/861 , H04L12/911
摘要： PROBLEM TO BE SOLVED: To provide a packet queuing device and method enabling high transfer speed, large buffer capacity and not large scale circuit. SOLUTION: The packet queuing device 1 stores a packet to be received by a WAN side receiving section 11 in an external buffer memory 61, and stores a packet to be received by LAN side receiving sections 41-1 to 4 in an internal buffer memory 50. In addition, both packets are controlled by the same QoS control section 31, the packet stored in an external buffer storage section 61 is transmitted from LAN side transmitting sections 56-1 to 4 without being stored in an internal buffer storage section 50. Thus, the packet stored in the external buffer storage section 61 is transferred to the internal buffer storage section 50 while using buffers having transfer rate and buffer capacity according to the receiving sections to prevent generation of packet overflow. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够实现高传输速度，大缓冲器容量和不大规模电路的分组排队装置和方法。解决方案：分组排队装置1将要由WAN侧接收部分11接收的分组存储在外部缓冲存储器61中，并将要由LAN侧接收部分41-1至4接收的分组存储在内部此外，两个分组由相同的QoS控制部分31控制，存储在外部缓冲存储部分61中的分组从LAN侧发送部分56-1至4发送，而不被存储在内部缓冲存储部分因此，存储在外部缓冲存储部分61中的分组被传送到内部缓冲存储部分50，同时使用根据接收部分的具有传输速率和缓冲器容量的缓冲器来防止分组溢出的产生。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2011009876A Buffer circuit and buffer circuit control method 有权
标题翻译：缓冲电路和缓冲电路控制方法
公开(公告)号：JP2011009876A
公开(公告)日：2011-01-13
申请号：JP2009149094
申请日：2009-06-23
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA TAKAKUNI , KOIKE KEIICHI , OYAMA KATSUICHI , HASHIMOTO MASATAKA
IPC分类号： H04L12/931 , H04L12/933
摘要： PROBLEM TO BE SOLVED: To provide a buffer circuit with high efficiency of using a memory for a buffer, and to provide a buffer circuit control method.SOLUTION: The buffer circuit includes: a memory means for the buffer storing frame data; a storage-amount-for-each-attribute-value monitoring means for output of a storage amount for each attribute value indicating the number of the frame data stored in the memory means for the buffer for each attribute of the frame data; a storage decision means for calculating the upper limit amount of the storage amount for each attribute value on the basis of the free capacity of the memory means for the buffer or the storage amount or the increase and decrease, comparing the storage amount for each attribute value with the upper limit amount of the storage amount for each attribute value when the attribute value indicating the attribute of the frame data is input, determining whether to store the frame data of the attribute value in the memory means for the buffer, and for output of information indicating storage presence when storing them; and a memory-for-buffer control means for writing the frame data to the memory means for the buffer when the frame data is input and the information of the storage presence is input from the storage decision means.
摘要翻译：要解决的问题：提供一种使用缓冲器存储器的高效率的缓冲电路，并提供缓冲电路控制方法。解决方案：缓冲电路包括：缓冲器存储帧数据的存储装置; 用于每个属性值监视装置的存储量，用于输出每个属性值的存储量，所述属性值指示存储在所述帧数据的每个属性的所述缓冲器的存储装置中的帧数据的数量; 存储判定装置，用于根据缓冲器的存储装置的可用容量或存储量或增减来计算每个属性值的存储量的上限量，比较每个属性值的存储量当指示了帧数据的属性的属性值被输入时，确定是否将属性值的帧数据存储在缓冲器的存储装置中，并且为了输出指示存储时的存储信息的信息; 以及用于缓冲存储器的控制装置，用于当帧数据被输入并且从存储决定装置输入存储存在的信息时，将帧数据写入缓冲器的存储装置。

5. 发明专利

JP2011055370A Circuit and method for processing communication 有权
标题翻译：用于处理通信的电路和方法
公开(公告)号：JP2011055370A
公开(公告)日：2011-03-17
申请号：JP2009204064
申请日：2009-09-03
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA TAKAKUNI , KOIKE KEIICHI , OYAMA KATSUICHI
IPC分类号： H04L12/701 , H04L12/70 , H04L12/775
摘要： PROBLEM TO BE SOLVED: To provide a circuit and method for processing communication capable of performing determination of processes adapting to a reception frame in parallel, and suppressing increase of power consumption due to supply of a clock signal. SOLUTION: This circuit for processing communication includes: an analysis section 12 for analyzing a reception frame; search/determination sections 17-1 to 17-N for performing determination of processes adapting to a reception frame in parallel; a clock supply section 14 for supplying a clock signal to the search/determination sections; and a search/determination section selection section 13 for selecting one of the search/determination sections when analysis information is input from the analysis section 12. When one search/determination section 17-i (i is a positive integer satisfying 1≤i≤N) is selected from the search/determination sections, the search/determination section selection section 13 controls the clock supply section 14 to supply the clock signal to the search/determination section 17-i, and controls the clock supply section 14 to stop the supply of the clock signal after the search/determination section 17-i completes search. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于处理能够并行地执行适合于接收帧的处理的确定的通信的电路和方法，并且抑制由于提供时钟信号而造成的功耗的增加。解决方案：用于处理通信的电路包括：用于分析接收帧的分析部分12; 搜索/确定部分17-1至17-N，用于并行地确定适应于接收帧的处理; 时钟提供部分14，用于向搜索/确定部分提供时钟信号; 以及搜索/确定部分选择部分13，用于在从分析部分12输入分析信息时选择搜索/确定部分之一。当一个搜索/确定部分17-i（i是满足1≤i≤N的正整数）从搜索/确定部分中选择时，搜索/确定部分选择部分13控制时钟提供部分14将时钟信号提供给搜索/确定部分17-i，并且控制时钟提供部分14停止供应在搜索/确定部分17-i完成搜索之后的时钟信号。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2011004083A Communication quality control device and communication quality control method 有权
标题翻译：通信质量控制设备和通信质量控制方法
公开(公告)号：JP2011004083A
公开(公告)日：2011-01-06
申请号：JP2009144589
申请日：2009-06-17
申请人： Nippon Telegr & Teleph Corp , Ntt Electornics Corp , Nttエレクトロニクス株式会社 , 日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KAWAI KENJI , KOIKE KEIICHI , OYAMA KATSUICHI , NOUCHI HIROYUKI
IPC分类号： H04L12/815 , H04L12/863 , H04L12/865 , H04L12/867 , H04L29/06
摘要： PROBLEM TO BE SOLVED: To provide a communication quality control device and a communication quality control method capable of reducing a circuit scale and improving the accuracy of scheduling.SOLUTION: In a queue decision part 9, packet information is queued in a specified queue. In a scheduling circuit 10, a comparison value for selecting an input is prepared from a transmission request, a quotient, a round robin value and a value of priority, the input having the smallest comparison value for selecting the input is obtained and a frame length and the transmission request are transmitted to a packet reader 11. In the packet reader 11, a packet is read from a packet buffer 7 according to packet information obtained from the queue 8, and the packet is transmitted to a transmitter 12. In the scheduling circuit 10, a dividend coupling the residual of the input having a minimum value with the frame length of the packet requesting the transmission is divided by the weight of the input, and the quotient and the residual are updated for computing the next comparison value for selecting the input.
摘要翻译：要解决的问题：提供能够减小电路规模并提高调度精度的通信质量控制装置和通信质量控制方法。解决方案：在队列决定部分9中，分组信息在指定队列中排队。在调度电路10中，从发送请求，商，循环值和优先级值准备用于选择输入的比较值，获得用于选择输入的具有最小比较值的输入，并且获得帧长度并且发送请求被发送到分组读取器11.在分组读取器11中，根据从队列8获得的分组信息，从分组缓冲器7读取分组，并将分组发送到发送机12.在调度中电路10，将具有最小值的输入的残差与请求传输的分组的帧长度相除的余数除以输入的权重，并且更新商和残差以计算下一个比较值以进行选择输入。

7. 发明专利

JP2014115758A Information processing device and information processing program 有权
标题翻译：信息处理设备和信息处理程序
公开(公告)号：JP2014115758A
公开(公告)日：2014-06-26
申请号：JP2012268006
申请日：2012-12-07
申请人： Nippon Telegr & Teleph Corp , 日本電信電話株式会社
发明人： ANDO MASARU , NISHIDA TAKAKUNI , KOIKE KEIICHI , SATO ATSUSHI , KATAYAMA YUKIHISA
IPC分类号： G06F9/50
摘要： PROBLEM TO BE SOLVED: To suppress degradation of throughput of a hardware function executing specific processing in a device in which a plurality of bundles of software modules operate.SOLUTION: A bundle is registered in a bundle management table 13 with information indicating whether the bundle uses a hardware (HW) function 17. When bundle management means 12 registers a new bundle in the bundle management table, the bundle management means 12 compares the total number of bundles which use the HW function with the maximum number of bundles authorized to use the HW function, registers the new bundle as a bundle authorized to use the HW function when the total number of bundles which use the HW function is less than the maximum number of bundles authorized to use the HW function, and registers the new bundle as a bundle unauthorized to use the HW function when the total number reaches the maximum number. Thus, even if many bundles require to use the HW function 17, the number of the bundles authorized to use the HW function 17 is restricted, so that it is possible to prevent an increase in overhead due to use switch-over of the HW function 17 or contention for the HW function 17.
摘要翻译：要解决的问题：为了抑制在多个软件模块捆绑的装置中执行特定处理的硬件功能的吞吐量的劣化。解决方案：在捆绑管理表13中注册捆绑，其中指示捆是否使用硬件（HW）功能17.当捆绑管理装置12在捆绑管理表中登记新捆绑包时，捆绑管理装置12将使用HW功能的捆绑的总数与授权使用HW的捆绑的最大数量进行比较功能，当使用HW功能的捆绑包总数小于授权使用HW功能的捆绑包的最大数量时，将新捆绑包注册为授权使用HW功能的捆绑包，并将新捆绑包注册为捆绑包未经授权当总数达到最大数量时使用HW功能。因此，即使许多束要求使用HW功能17，限制了授权使用HW功能17的束的数量，从而可以防止由于HW功能的切换而引起的开销增加 17或HW功能的争用17。

8. 发明专利

JP2014160911A Packet processing device, method, and program 审中-公开
标题翻译：分组处理设备，方法和程序
公开(公告)号：JP2014160911A
公开(公告)日：2014-09-04
申请号：JP2013030025
申请日：2013-02-19
申请人： Nippon Telegr & Teleph Corp , 日本電信電話株式会社
发明人： NISHIDA TAKAKUNI , KOIKE KEIICHI , OKAMOTO MANABU , SATO ATSUSHI
IPC分类号： H04M3/00 , H04L12/70 , H04L12/823 , H04L12/841 , H04W28/14
摘要： PROBLEM TO BE SOLVED: To improve quality of voice communication by packet communication using a radio network, by reducing the number of discontinuous points in voice in reproducing burst-transferred voice packets.SOLUTION: A discard determination unit 20 compares an interval between reception time of current reception packets and reception time of preceding reception packets with allowable delay time set in advance, every time packets are received; calculates the number of discarded packets on the basis of difference between the packet reception interval and the allowable delay time and a packet transmission interval set in advance, when the packet reception interval exceeds the allowable delay time; takes packets whose number corresponds to the calculated number of discarded packets as discard candidates from the current reception packets, and discards packets whose sound pressure is equal to or lower than a threshold of the discard candidates.
摘要翻译：要解决的问题：为了通过使用无线网络的分组通信来提高语音通信的质量，通过减少再现突发传送的语音分组中的语音中的不连续点的数量。解决方案：丢弃确定单元20将接收时间每次接收到数据包时，预先设定允许延迟时间的接收数据包的当前接收数据包和接收时间; 当分组接收间隔超过允许延迟时间时，基于分组接收间隔和可允许延迟时间之间的差异以及预先设置的分组传输间隔来计算丢弃分组的数量; 从当前接收包中取出与计算出的丢弃数据包数相对应的数据包作为丢弃候选，并丢弃其声压等于或低于丢弃候选的阈值的数据包。

9. 发明专利

JP2013251688A Network connection confirmation system 有权
标题翻译：网络连接确认系统
公开(公告)号：JP2013251688A
公开(公告)日：2013-12-12
申请号：JP2012124376
申请日：2012-05-31
申请人： Nippon Telegr & Teleph Corp , 日本電信電話株式会社
发明人： HIRAGA TAKAICHI , NISHIDA TAKAKUNI , KOIKE KEIICHI , SATO ATSUSHI
IPC分类号： H04L12/70 , H04L29/14 , H04M11/00
摘要： PROBLEM TO BE SOLVED: To provide a network connection confirmation system capable of performing support for certain cause specification at an occurrence of troubles in access from a user terminal connected to a network to a server connected to the same network.SOLUTION: A confirmation stick terminal comprises a transmission part for generating confirmation information packet including user identification information and numerical value information designated by the user, and transmitting the confirmation information packet to an automatic voice response terminal via an IP network. The automatic voice response terminal comprises: a storage part for storing the user identification information transmitted from a user telephone machine via a telephone network; and a response part for making the user telephone machine output the numerical value information in the confirmation information packet by voice via the telephone network in the case where the user identification information included in the confirmation information packet transmitted from the confirmation stick terminal is stored in the storage part.
摘要翻译：要解决的问题：提供一种网络连接确认系统，其能够在从连接到网络的用户终端到连接到同一网络的服务器的访问中发生故障时执行对某些原因指定的支持。解决方案：确认棒终端包括用于产生包括由用户指定的用户识别信息和数值信息的确认信息分组的发送部分，并且经由IP网络将确认信息分组发送到自动语音响应终端。自动语音响应终端包括：存储部分，用于存储经由电话网络从用户电话机发送的用户识别信息; 以及响应部分，用于使用户电话机在从确认棒终端发送的确认信息分组中包含的用户识别信息存储在用户电话机中的情况下，经由电话网络通过语音输出确认信息分组中的数值信息存储部分。

10. 发明专利

JP2010266751A Circuit for generating extended key for encryption, circuit for generating extended key for decryption, method for generating extended key for encryption, and method for generating extended key for decryption 有权
标题翻译：用于生成用于加密的扩展密钥的电路，用于生成用于解密的扩展密钥的电路，用于生成用于加密的扩展密钥的生成方法以及用于生成用于解密的扩展密钥的方法
公开(公告)号：JP2010266751A
公开(公告)日：2010-11-25
申请号：JP2009118956
申请日：2009-05-15
申请人： Nippon Telegr & Teleph Corp , 日本電信電話株式会社
发明人： KAWAI KENJI , NISHIDA TAKAKUNI , KOIKE KEIICHI
IPC分类号： G09C1/00
摘要： PROBLEM TO BE SOLVED: To perform encryption/decryption without increasing a circuit scale even when the number of SAs (Security Associations) being the object of an IPsec circuit increases. SOLUTION: An extended key for encryption generating logic circuit 121 stores, when starting generation of an extended key for encryption, the input value in an extended key for encryption generating register 122 and, when an AES encryption circuit performs each round processing, performs a prescribed extended key for encryption generating operation determined in accordance with key length information indicating the length of an encryption key and the progress of the round processing to the value stored by the extended key for encryption generating register 122, and updates the value stored by the extended key for encryption generating register 122 in accordance with the result of the extended key for encryption generating operation. An extended key for encryption outputting logic circuit 123 outputs, as an extended key for encryption, the value of 128 bit length selected from the extended key for encryption generating register 122 on the basis of the key length information and the progress of the round processing. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：即使当作为IPsec电路的对象的SA（安全关联）的数量增加时，即使不增加电路规模来执行加密/解密。解密：加密生成逻辑电路121的扩展密钥在开始生成用于加密的扩展密钥时，存储用于加密生成寄存器122的扩展密钥中的输入值，并且当AES加密电路执行每个循环处理时，执行根据表示加密密钥的长度的密钥长度信息确定的加密生成操作的规定的扩展密钥以及由加密生成寄存器122的扩展密钥存储的值的轮回处理的进度，并更新由根据用于加密生成操作的扩展密钥的结果的加密生成寄存器122的扩展密钥。用于加密输出逻辑电路123的扩展密钥根据密钥长度信息和循环处理的进度输出从加密生成寄存器122的扩展密钥中选择的128位长度的值作为加密的扩展密钥。版权所有（C）2011，JPO＆INPIT

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