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4. 发明专利

JP2013033786A Semiconductor device and semiconductor device manufacturing method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2013033786A
公开(公告)日：2013-02-14
申请号：JP2011168021
申请日：2011-08-01
申请人： Sony Corp , ソニー株式会社
发明人： AOYANAGI KENICHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L27/14 , H01L27/146
CPC分类号： H01L2224/05547 , H01L2224/08121 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a three-dimensional structure, which ensures a bonding force with preventing diffusion of an electrode material in a configuration where electrodes are bonded by bonding of two substrates thereby to achieve improvement of reliability.SOLUTION: A semiconductor device comprises: a first substrate 2 including a first electrode 33, and a first insulation film 35 composed of a diffusion prevention material of the first electrode 33 and covering around the first electrode 33, in which a bonding surface 41 is composed of the first electrode 33 and the first insulation film 35; and a second substrate 7 bonded to the first substrate 2 and including a second electrode 67 bonded to the first electrode 33, and a second insulation film 69 composed of a diffusion prevention material of the second electrode 67 and covering around the second electrode 67, in which a bonding surface 71 opposed to the first substrate 2 is composed of the second electrode 67 and the second insulation film 69.
摘要翻译：解决的问题：提供一种具有三维结构的半导体器件，其确保了通过两个基板的接合来结合电极的结构中的电极材料的扩散的结合力，从而实现可靠性的提高。解决方案：半导体器件包括：包括第一电极33的第一基板2和由第一电极33的防扩散材料构成并围绕第一电极33覆盖的第一绝缘膜35，其中接合表面 41由第一电极33和第一绝缘膜35构成; 以及第二基板7，其接合到第一基板2并且包括接合到第一电极33的第二电极67，以及由第二电极67的防扩散材料构成并围绕第二电极67覆盖的第二绝缘膜69 与第一基板2相对的接合面71由第二电极67和第二绝缘膜69构成。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JPS6130059A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS6130059A
公开(公告)日：1986-02-12
申请号：JP15059884
申请日：1984-07-20
申请人： Nec Corp
发明人： YASUMOTO MASAAKI , HAYAMA HIROSHI , ENOMOTO TADAYOSHI
IPC分类号： H01L25/00 , H01L21/18 , H01L21/60 , H01L21/68 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/00
CPC分类号： H01L21/187 , H01L21/6835 , H01L21/8221 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/08145 , H01L2224/1147 , H01L2224/13144 , H01L2224/73104 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/81121 , H01L2224/8121 , H01L2224/81815 , H01L2224/81894 , H01L2224/8319 , H01L2224/838 , H01L2225/06513 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01039 , H01L2924/01072 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , Y10S148/164 , H01L2224/29099 , H01L2924/00
摘要： PURPOSE:To shorten a product-manufacturing term, by a method in which each two of circuit substrates having active layers, insulating layers and metal bumps are combined with the bumps contacted respectively, and then the resulted combinations are stacked, in a case where the circuit substrates having different functions are stacked to make a multi-layer IC. CONSTITUTION:An active layer 102 having an Al metal wiring is formed over a substrate 101 such as an insulator. An SiO2 film 103 is coated thereon and is bored with a required number of openings using photo etching. After metal bumps 104 contacting with the layer 102 are buried therein, insulating adhesive 105 such as polyimide resin is coated thereon thickly and is polished to expose the surfaces of the bumps 104. Thus a first circuit substrate 150 is provided which is buried with the adhesive 150 between the bumps 104 and has a planar surface. Next, a second circuit substrate 151 formed in the same way is combined with the first substrate 150 with the bumps 104 and 104' contacted, and the two substrates are heated to be integrated. Such integrated combinations are stacked by a desired number according to the request to make multi-functional.
摘要翻译：目的：为了缩短产品制造期限，通过将具有有源层，绝缘层和金属凸块的两个电路基板与分别接触的凸块结合的方法，然后将所得到的组合层叠在一起，堆叠具有不同功能的电路基板以形成多层IC。构成：在诸如绝缘体的基板101上形成具有Al金属布线的有源层102。在其上涂覆SiO 2膜103，并且使用光蚀刻对所需数量的开孔进行钻孔。在与层102接触的金属凸块104被埋入其中之后，诸如聚酰亚胺树脂之类的绝缘粘合剂105被涂覆在其上并被抛光以暴露凸块104的表面。因此，提供了第一电路衬底150， 150之间，并且具有平坦表面。接下来，以相同的方式形成的第二电路基板151与第一基板150组合，凸块104和104'接触，并且将两个基板加热成一体。根据要进行多功能的要求，这种集成组合按期望的数量堆叠。

6. 发明专利

KR20210025156A KR20210025156A - Semiconductor device and method of manufacturing the same 审中-公开
公开(公告)号：KR20210025156A
公开(公告)日：2021-03-09
申请号：KR1020190104505A
申请日：2019-08-26
申请人： 삼성전자주식회사
发明人： 장주희 , 김석호 , 나훈주 , 박재형 , 이규하
IPC分类号： H01L27/146 , H01L21/52 , H01L21/768
CPC分类号： H01L24/08 , H01L27/1469 , H01L21/52 , H01L21/768 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/27 , H01L24/32 , H01L27/14612 , H01L27/14621 , H01L27/14627 , H01L27/14634 , H01L27/14636 , H01L2224/03831 , H01L2224/03845 , H01L2224/05018 , H01L2224/05022 , H01L2224/05026 , H01L2224/05073 , H01L2224/05149 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05547 , H01L2224/05557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05647 , H01L2224/05657 , H01L2224/05676 , H01L2224/0568 , H01L2224/05684 , H01L2224/08057 , H01L2224/08058 , H01L2224/08059 , H01L2224/0807 , H01L2224/08121 , H01L2224/08145 , H01L2224/32145 , H01L2224/80047 , H01L2224/80345 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/80986
摘要： 본 개시의 일 실시예는, 제1 기판과, 상기 제1 기판 상에 배치되며 평탄한 표면을 갖는 제1 절연층과, 상기 제1 절연층에 매립되어 상기 제1 절연층의 상기 표면과 실질적으로 평탄한 표면을 갖는 제1 전극과, 상기 제1 절연층과 상기 제1 전극 사이에 배치된 제1 배리어를 갖는 제1 반도체 칩 및, 제2 기판과, 상기 제2 기판 하부에 배치되며 평탄한 표면을 갖는 제2 절연층과, 상기 제2 절연층에 매립되어 상기 제2 절연층의 상기 표면과 실질적으로 평탄한 표면을 갖는 제2 전극과, 상기 제2 절연층과 상기 제2 전극 사이에 배치된 제2 배리어를 갖는 제2 반도체 칩을 포함하며, 상기 제1 절연층 및 상기 제2 절연층의 표면들이 접합되어 상기 제1 전극 및 상기 제2 전극이 연결되고, 상기 제1 절연층은 상기 접합 계면에 인접한 상기 제1 전극의 일 측면 영역에 접촉되는 부분을 갖는 반도체 장치를 제공한다.

7. 发明专利

JP2017135397A 電子部品実装方法および電子部品実装システム审中-公开
公开(公告)号：JP2017135397A
公开(公告)日：2017-08-03
申请号：JP2017050510
申请日：2017-03-15
申请人：ボンドテック株式会社
发明人：山内朗
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18 , H01L21/60 , H05K3/34 , H01L21/52
CPC分类号： H01L25/50 , H01L21/67144 , H01L21/6835 , H01L24/75 , H01L24/80 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L2221/68354 , H01L2221/68381 , H01L2224/0401 , H01L2224/05571 , H01L2224/05647 , H01L2224/08145 , H01L2224/13023 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/75315 , H01L2224/75753 , H01L2224/7598 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/81191 , H01L2224/81201 , H01L2224/81815 , H01L2224/8183 , H01L2224/83 , H01L2224/94 , H01L2224/95001 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L24/13 , H01L24/81 , H01L24/83 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/10253 , H01L2924/15788 , H01L2924/3511
摘要：【課題】複数の電子部品を基板上に平面配置して実装することをさらに容易に実現することが可能な実装技術を提供する。【解決手段】基板WA上に複数のチップCP1が平面配置されて積層される。次に、仮基板WT2上に形成された樹脂層RS2に、チップCP1上に実装する第2層の複数のチップCP2がフェイスアップ状態で平面配置され仮固定される。そして、仮基板WT2の上下を反転して第2層の複数のチップCP2をフェイスダウン状態で仮基板WT2に保持し、基板WAと仮基板WT2とを位置合わせしながら、第2層の各チップCP2と基板WA上の第1層の各チップCP1とが相対的に接近させ、各チップCP1と各チップCP2とが接合する。さらに、各チップCP2が各チップCP1に接合された状態を維持しつつ、第2層の複数のチップCP2から仮基板WT2が分離される。上記工程を繰り返して積層体を得る。【選択図】図22

10. 发明专利

JP5346063B2 Method bonded by molecular bonding, including compensation for radial position deviation 有权
公开(公告)号：JP5346063B2
公开(公告)日：2013-11-20
申请号：JP2011133018
申请日：2011-06-15
申请人：ソイテック
发明人：ゴーダングウェルタツ
IPC分类号： H01L21/02 , H01L21/683
CPC分类号： H01L21/185 , B32B37/144 , B32B37/18 , B32B38/1808 , B32B38/1866 , B32B41/00 , B32B2041/04 , B32B2307/202 , B32B2309/72 , B32B2457/14 , H01L21/187 , H01L24/75 , H01L24/80 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/08146 , H01L2224/75702 , H01L2224/75703 , H01L2224/75756 , H01L2224/75901 , H01L2224/80006 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/80948 , H01L2224/94 , H01L2924/3511 , Y10T156/10 , Y10T156/1089 , Y10T156/1092 , H01L2224/80
摘要： The method involves bringing two plates (100, 200) e.g. silicon circular plates, into contact, so as to initiate propagation of a bonding wave between the two plates. A predefined bonding curvature is imposed on one of the two plates by a membrane during the contacting step, where the membrane is interposed between the former plate and a holding support (310). The other plate is free to adapt to the predefined bonding curvature imposed on the former plate, during the propagation of the bonding wave. An independent claim is also included for an apparatus for bonding plates by molecular adhesion.

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