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91. 发明授权

US07979483B1 Multiplexed proportional-integral-derivative filter architecture (Mux-PID) for control-loop applications 有权
标题翻译：用于控制环应用的多路比例积分微分滤波器架构（Mux-PID）
公开(公告)号：US07979483B1
公开(公告)日：2011-07-12
申请号：US11506189
申请日：2006-08-16
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： G06F17/10
CPC分类号： G05B11/42
摘要： A multiplexed digital proportional-integral-derivative filter receives error signal samples and operates in different states during sub-cycles of a single system cycle. A single multiplier and a single adder within the filter calculate at least portions of a proportional control signal, an integral control signal and a derivative control signal for one error signal sample during successive sub-cycles. The calculated control signal portions are aggregated to produce a filtered error signal for the respective error signal sample. The original resolution at lower cost, or increased resolution at the original cost, are achieved, as well as full programmability of loop gain with only negligible increase in loop latency.
摘要翻译：复用的数字比例积分微分滤波器接收误差信号采样并在单个系统周期的子周期期间以不同的状态操作。滤波器内的单个乘法器和单个加法器在连续的子周期期间计算一个误差信号采样的比例控制信号，积分控制信号和微分控制信号的至少一部分。所计算的控制信号部分被聚合以产生用于相应误差信号样本的滤波误差信号。以较低的成本或原始成本提高分辨率的原始分辨率，以及环路增益的全面可编程性，环路延迟增加可忽略不计。

92. 发明申请

US20110163457A1 INTEGRATED CIRCUIT MICRO-MODULE 有权
标题翻译：集成电路微型模块
公开(公告)号：US20110163457A1
公开(公告)日：2011-07-07
申请号：US13022392
申请日：2011-02-07
申请人： Anuraag Mohan , Peter Smeys
发明人： Anuraag Mohan , Peter Smeys
IPC分类号： H01L23/50 , H01L21/50
CPC分类号： H01L24/97 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3121 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5385 , H01L23/5389 , H01L23/66 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/16 , H01L2221/68377 , H01L2223/6677 , H01L2224/24137 , H01L2224/24227 , H01L2224/2518 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01087 , H01L2924/014 , H01L2924/07802 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H05K1/165 , H05K1/185 , H05K2201/10098 , H05K2203/1469 , H01L2224/82 , H01L2924/00
摘要： One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.
摘要翻译：本发明的一个方面涉及一种集成电路封装，该集成电路封装包括在衬底上形成的多层平坦化，光可成像环氧树脂。在一些设计中，衬底是硅晶片。集成电路嵌入在环氧树脂中。通过互连层电耦合到集成电路的有源面的天线在一个环氧树脂层上形成。在各种实施例中，环氧树脂层中的至少一些位于衬底和天线之间，使得在衬底和天线之间存在至少约100微米的距离。

93. 发明授权

US07960222B1 System and method for manufacturing double EPI N-type lateral diffusion metal oxide semiconductor transistors 有权
标题翻译：制造双EPI N型横向扩散金属氧化物半导体晶体管的系统和方法
公开(公告)号：US07960222B1
公开(公告)日：2011-06-14
申请号：US11986498
申请日：2007-11-21
申请人： Taehun Kwon
发明人： Taehun Kwon
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/823418 , H01L21/823456 , H01L21/823493 , H01L27/0921 , H01L27/0928 , H01L29/0653 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/66681 , H01L29/7817
摘要： A system and a method are disclosed for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors. In one embodiment two N-type buried layers are used to minimize the operation of a parasitic PNP bipolar transistor. The use of two N-type buried layers increases the base width of the parasitic PNP bipolar transistor without significantly decreasing the peak doping profiles in the two N-type buried layers. In one embodiment two N-type buried layers and one P-type buried layer are used to form a protection NPN bipolar transistor that minimizes the operation of parasitic NPN bipolar transistor. The N-type lateral diffusion metal oxide semiconductor transistors of the invention are useful in inductive full load or half bridge converter circuits that drive very high current.
摘要翻译：公开了用于制造双外延层N型横向扩散金属氧化物半导体晶体管的系统和方法。在一个实施例中，使用两个N型掩埋层来最小化寄生PNP双极晶体管的操作。使用两个N型掩埋层增加了寄生PNP双极晶体管的基极宽度，而不会明显降低两个N型掩埋层中的峰值掺杂分布。在一个实施例中，使用两个N型掩埋层和一个P型掩埋层来形成使寄生NPN双极晶体管的操作最小化的保护NPN双极晶体管。本发明的N型横向扩散金属氧化物半导体晶体管可用于驱动非常高的电流的感应全负载或半桥转换器电路。

94. 发明申请

US20110115395A1 DIMMER DECODER WITH IMPROVED EFFICIENCY FOR USE WITH LED DRIVERS 有权
标题翻译：具有提高效率的DIMMER解码器与LED驱动器一起使用
公开(公告)号：US20110115395A1
公开(公告)日：2011-05-19
申请号：US12904535
申请日：2010-10-14
申请人： Steven M. Barrow , James H. Masson , Daniel R. Herrington , Irwin R. Nederbragt , Chi Yuen Lai
发明人： Steven M. Barrow , James H. Masson , Daniel R. Herrington , Irwin R. Nederbragt , Chi Yuen Lai
IPC分类号： H05B41/16
CPC分类号： H05B33/0815 , H05B33/0845 , Y02B20/346
摘要： A method includes receiving a sense signal having multiple pulses, where the sense signal is based on an output of a dimmer. The method also includes, for each of multiple sampling periods, sampling a subset of the pulses in the sense signal during that sampling period. The method further includes generating a holding current for the dimmer during the sampling of the subset of pulses in at least one of the sampling periods. In addition, the method includes, for each of the sampling periods, generating an output value identifying a duty cycle for driving one or more light emitting diodes (LEDs). The subset of pulses in each of the sampling periods includes multiple pulses during that sampling period but not one or more initial pulses at a beginning of that sampling period.
摘要翻译：一种方法包括接收具有多个脉冲的感测信号，其中感测信号基于调光器的输出。对于多个采样周期中的每一个，该方法还包括在该采样周期期间对感测信号中的脉冲的子集进行采样。该方法还包括在至少一个采样周期中对脉冲子集进行采样期间产生用于调光器的保持电流。此外，对于每个采样周期，该方法包括产生识别用于驱动一个或多个发光二极管（LED）的占空比的输出值。每个采样周期中的脉冲子集在该采样周期期间包括多个脉冲，而在该采样周期的开始处不包括一个或多个初始脉冲。

95. 发明授权

US07932754B1 Optimal control of charge-modulated gate drivers 有权
标题翻译：电荷调制栅极驱动器的最优控制
公开(公告)号：US07932754B1
公开(公告)日：2011-04-26
申请号：US11506335
申请日：2006-08-17
申请人： Michael Eugene Broach , Michael D. Mulligan
发明人： Michael Eugene Broach , Michael D. Mulligan
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： H03K17/0822 , H02M1/08 , H02M3/1588 , H03K17/145 , H03K17/166 , H03K2217/0036 , Y02B70/1466
摘要： A system, apparatus and method is arranged to adaptively adjust drive signals for a gate controlled switch circuit such that the amount of gate swing automatically changes based on the load conditions. An adaptive gate charge modulation (GCM) technique can be utilized to dynamically adjust the drive signals so that a substantially constant voltage drop is perceived across to a gate controlled switch circuit. The voltage drop across the gate controlled switch circuit can be set to a reference level that is adjusted whenever a change in system conditions are detected. The gate charge can then be adaptively increased and decreased during operation, within maximum and minimum limits, to substantially match the voltage drop of the gate control switch circuit to the reference level.
摘要翻译：一种系统，装置和方法被设置为自适应地调整门控开关电路的驱动信号，使得门摆动量基于负载条件自动改变。可以利用自适应栅极电荷调制（GCM）技术来动态地调整驱动信号，从而在栅极控制的开关电路两端感知到基本恒定的电压降。门控制开关电路两端的电压降可以设置为每当检测到系统条件发生变化时调整的参考电平。然后可以在最大和最小限度内的操作期间自适应地增加和减小栅极电荷，以使栅极控制开关电路的电压降达到基准电平。

96. 发明授权

US07932709B1 Stable high efficiency step-up voltage regulator with fast transient response and ultra low output voltage ripple 有权
标题翻译：稳定的高效率升压稳压器具有快速瞬态响应和超低输出电压纹波
公开(公告)号：US07932709B1
公开(公告)日：2011-04-26
申请号：US12147474
申请日：2008-06-26
申请人： Hok Sun Ling
发明人： Hok Sun Ling
IPC分类号： G05F1/575
CPC分类号： H02M3/156
摘要： A regulator circuit and a method of generating a stable, low-ripple output, step-up or step-down voltage are disclosed. A low ESR (Equivalent Series Resistance) output capacitor is employed to provide low output voltage ripple. A voltage, −VESRi, is generated using information based on an input voltage and the output voltage. −VESRi is coupled onto an intermediate reference voltage generated by an integrator based on the output voltage and a constant reference voltage, to form another voltage, VREFi. VREFi is coupled to an input of a feedback comparator, instead of a plain constant reference voltage, to modulate the duty cycle of a main switch. The output voltage is inputted as a feedback signal to another input of the feedback comparator. −VESRi, is generated using information based on an input voltage and the output voltage in such a way that output voltage is stable without sub-harmonic oscillation.
摘要翻译：公开了调节器电路和产生稳定的低纹波输出，升压或降压的方法。使用低ESR（等效串联电阻）输出电容器来提供低输出电压纹波。使用基于输入电压和输出电压的信息生成电压-VESRi。 -VESRi基于输出电压和恒定参考电压耦合到由积分器产生的中间参考电压，以形成另一电压VREFi。 VREFi耦合到反馈比较器的输入而不是普通参考电压，以调制主开关的占空比。输出电压作为反馈信号输入到反馈比较器的另一输入端。 -VESRi使用基于输入电压和输出电压的信息，使得输出电压稳定而没有亚谐波振荡的方式产生。

97. 发明申请

US20110089914A1 Apparatus and method for isolating an adaptive voltage scaling (AVS) loop in a powered system 审中-公开
标题翻译：用于在动力系统中隔离自适应电压缩放（AVS）回路的装置和方法
公开(公告)号：US20110089914A1
公开(公告)日：2011-04-21
申请号：US12587910
申请日：2009-10-15
申请人： Mark Hartman
发明人： Mark Hartman
IPC分类号： G05F1/10
CPC分类号： G06F1/26
摘要： A method includes generating a regulated voltage for a powered component and modifying the regulated voltage with an adaptive voltage scaling (AVS) control loop. The method also includes further modifying the regulated voltage using at least one additional control loop. The AVS control loop is isolated from the at least one additional control loop. Modifying the regulated voltage with the AVS control loop could include storing an AVS digital value and converting the AVS digital value into an analog signal. Modifying the regulated voltage with the AVS control loop could also include modifying a control signal for a voltage regulator using the analog signal, where the voltage regulator generates the regulated voltage. Modifying the regulated voltage with the AVS control loop could further include buffering the analog signal and outputting the buffered analog signal as an isolated AVS signal over the AVS control loop.
摘要翻译：一种方法包括产生用于有源部件的调节电压并用自适应电压调节（AVS）控制环来修改调节电压。该方法还包括使用至少一个附加控制回路来进一步修改调节电压。 AVS控制回路与至少一个附加控制回路隔离。使用AVS控制环来修改调节电压可能包括存储AVS数字值并将AVS数字值转换为模拟信号。使用AVS控制环修改调节电压还可以包括使用模拟信号修改电压调节器的控制信号，其中电压调节器产生调节电压。使用AVS控制回路修改调节电压可进一步包括缓冲模拟信号，并通过AVS控制回路输出缓冲模拟信号作为隔离的AVS信号。

98. 发明授权

US07930334B1 Gain control coding within proportional-integral-derivative filters for control-loop applications 有权
标题翻译：用于控制环应用的比例积分微分滤波器内的增益控制编码
公开(公告)号：US07930334B1
公开(公告)日：2011-04-19
申请号：US11731962
申请日：2007-04-02
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： G06F17/10
CPC分类号： G05B11/42
摘要： Proportional, integral and derivative error gains within a proportional-integral-derivative filter are selected based on a magnitude of the error value and with successively higher gain values corresponding to larger ranges of error values. Coding of the error gains is selected based on one or more of: large code-dynamic-range to achieve good transient and quiescent responses; small code-step ratio to achieve smooth transitions between consecutive steps; large gain control range to satisfy the differing gain coverage requirements of the three proportional, integral and derivative error; positive and negative code symmetry with small step increment about zero; reservation of code space for dead band elimination; allocation of code space to prevent overflow/underflow during multiplying and bit-shifting; and minimum cost and power.
摘要翻译：基于比例积分微分滤波器中的比例积分和微分误差增益是基于误差值的大小以及对应于较大范围误差值的连续较高增益值来选择的。基于以下一个或多个选择误差增益的编码：大代码 - 动态范围以实现良好的瞬态和静态响应; 小代码步长比实现连续步骤之间的平滑过渡; 大增益控制范围满足三种比例，积分和微分误差的不同增益覆盖要求; 正，负码对称，小步增量约零; 预留死区消除代码空间; 分配代码空间，以防止在乘法和位移期间的溢出/下溢; 最低成本和最低功耗。

99. 发明申请

US20110084607A1 Integrated driver system architecture for light emitting diodes (LEDS) 有权
标题翻译：用于发光二极管（LEDS）的集成驱动器系统架构
公开(公告)号：US20110084607A1
公开(公告)日：2011-04-14
申请号：US12925078
申请日：2010-10-13
申请人： Peter J. Hopper , Ann M. Gabrys , William French
发明人： Peter J. Hopper , Ann M. Gabrys , William French
IPC分类号： H01J7/44 , H05K1/18 , H05K3/10
CPC分类号： H05K1/165 , H05B33/0803 , H05B33/0815 , H05K1/162 , H05K1/186 , H05K2201/086 , H05K2201/10106
摘要： A method includes forming one or more capacitors over a substrate. The method also includes forming a transformer at least partially over the substrate. The transformer is adjacent to at least one of the one or more capacitors. At least a portion of the transformer is formed at a same level over the substrate as the one or more capacitors. The method further includes coupling the one or more capacitors and the transformer to at least one embedded integrated circuit die. The one or more capacitors, the transformer, and the at least one embedded integrated circuit die form at least part of a light emitting diode (LED) driver.
摘要翻译：一种方法包括在衬底上形成一个或多个电容器。该方法还包括至少部分地在衬底上形成变压器。变压器与一个或多个电容器中的至少一个相邻。所述变压器的至少一部分与所述一个或多个电容器形成在与所述衬底相同的电平上。该方法还包括将一个或多个电容器和变压器耦合到至少一个嵌入式集成电路管芯。一个或多个电容器，变压器和至少一个嵌入式集成电路管芯形成发光二极管（LED）驱动器的至少一部分。

100. 发明申请

US20110084407A1 SYSTEM AND METHOD FOR PREVENTING METAL CORROSION ON BOND PADS 审中-公开
标题翻译：用于防止金属腐蚀的粘合剂的系统和方法
公开(公告)号：US20110084407A1
公开(公告)日：2011-04-14
申请号：US12971513
申请日：2010-12-17
申请人： Rodney Hill
发明人： Rodney Hill
IPC分类号： H01L23/485
CPC分类号： H01L24/03 , H01L23/3157 , H01L24/05 , H01L2224/02166 , H01L2224/05554 , H01L2224/05599 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/14
摘要： A system and method are disclosed for preventing metal corrosion on bond pads. During manufacture of an integrated circuit device an anti-reflective coating (ARC) layer is applied to a metal stack of a bond pad. A mask and etch process is applied to etch an aperture through the ARC layer down to the metal stack. Then a passivation layer is applied to cover the ARC layer and the aperture through the ARC layer. Then another mask and etch process is applied to etch a bond pad opening through the passivation layer inside the ARC layer aperture down to the metal stack. Interior edge portions of the passivation layer seal the interior edge portions of the ARC layer aperture to prevent corrosion of the ARC layer due to high temperatures, high humidity and corrosive materials encountered in subsequent assembly operations of the integrated circuit device.
摘要翻译：公开了用于防止接合焊盘上的金属腐蚀的系统和方法。在集成电路器件的制造期间，将抗反射涂层（ARC）层施加到接合焊盘的金属堆叠。施加掩模和蚀刻工艺以将通过ARC层的孔蚀刻到金属堆叠。然后施加钝化层以覆盖ARC层和通过ARC层的孔。然后施加另一个掩模和蚀刻工艺以蚀刻通过ARC层孔内的钝化层的接合焊盘开口，直到金属堆叠。钝化层的内部边缘部分密封ARC层孔的内部边缘部分，以防止由于在集成电路器件的后续组装操作中遇到的高温，高湿度和腐蚀性材料导致的ARC层的腐蚀。

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