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91. 发明授权

US08144530B2 Semiconductor memory device and method for generating output enable signal 有权
标题翻译：半导体存储器件和产生输出使能信号的方法
公开(公告)号：US08144530B2
公开(公告)日：2012-03-27
申请号：US12494403
申请日：2009-06-30
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： H03L7/0816 , G11C7/1066 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
摘要翻译：半导体存储器件能够响应于读取命令和CAS延迟信息而产生输出使能信号。半导体存储器件包括：延迟锁定环，被配置为检测外部时钟信号和反馈时钟信号的相位差，产生对应于检测到的相位差的延迟控制信号，并通过延迟外部时钟信号产生DLL时钟信号延迟一段时间对应于延迟控制信号，延迟配置为响应于延迟控制信号而输出有效信号作为输出使能复位信号;以及输出使能信号发生器，其被配置为响应于输出使能复位信号复位;以及通过对外部时钟信号和DLL时钟信号进行计数，响应于读取信号和CAS等待时间信号产生输出使能信号。

92. 发明授权

US08143940B2 Internal supply voltage generating circuit and method for generating internal supply voltage 失效
标题翻译：内部电源电压发生电路及产生内部电源电压的方法
公开(公告)号：US08143940B2
公开(公告)日：2012-03-27
申请号：US12347605
申请日：2008-12-31
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56 , G11C5/145 , H03L7/0812 , H03L7/093
摘要： An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
摘要翻译：内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器被配置为产生具有与所述时钟比较器的输出信号相对应的电压电平的驱动控制电压; 以及配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。

93. 发明授权

US08045647B2 Low power, high speed receiver circuit for use in a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的低功率，高速接收电路
公开(公告)号：US08045647B2
公开(公告)日：2011-10-25
申请号：US12170254
申请日：2008-07-09
申请人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
发明人： Ic Su Oh , Kun Woo Park , Yong Ju Kim , Hee Woong Song , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： G11C7/1051 , G11C7/062 , G11C7/1069 , G11C11/56 , G11C27/026 , G11C2211/5634 , G11C2211/5642 , H04L25/0272 , H04L25/061 , H04L25/4919
摘要： A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
摘要翻译：根据本发明的接收机电路包括与第一时钟同步的第一相位传输单元，根据多个检测电平检测输入数据，并发送第一输出信号;第一放电控制单元，其控制第二相位传输单元，响应于第一输出信号，并且通过改变确定第二相位传输的输出的节点电位来调整第二相位传输单元的传输速度，并且与第二时钟同步的第二相位传输单元检测所述输入数据根据所述第一放电控制单元的输出，并发送第二输出信号。

94. 发明授权

US07969214B2 DLL circuit, update control apparatus in DLL circuit and update method of DLL circuit 有权
标题翻译： DLL电路，DLL电路中的更新控制装置和DLL电路的更新方法
公开(公告)号：US07969214B2
公开(公告)日：2011-06-28
申请号：US12493387
申请日：2009-06-29
申请人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
发明人： Jae Min Jang , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/085
摘要： A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled.
摘要翻译：延迟锁定环路（DLL）电路包括：相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号。更新控制装置被配置为通过响应于参考时钟信号确定第一逻辑值的数量和相位检测信号的第二逻辑值的数量之间的差异来产生有效间隔信号和更新控制信号。移位寄存器，被配置为当有效间隔信号被使能时响应于更新控制信号来更新授予延迟线的延迟值。

95. 发明授权

US07952364B2 Power noise detecting device and power noise control device using the same 失效
标题翻译：功率噪声检测装置和功率噪声控制装置使用相同
公开(公告)号：US07952364B2
公开(公告)日：2011-05-31
申请号：US12332294
申请日：2008-12-10
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G01R29/26
CPC分类号： H03H1/0007 , H03K19/00346
摘要： A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.
摘要翻译：电力噪声检测装置包括多个电力线，以及电力噪声检测部，被配置为通过整流多个电力线的电压并将整流电压转换为有效电压来检测电力噪声。

96. 发明授权

US07936620B2 Receiver of semiconductor memory apparatus 有权
标题翻译：半导体存储器的接收器
公开(公告)号：US07936620B2
公开(公告)日：2011-05-03
申请号：US12483413
申请日：2009-06-12
申请人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.
摘要翻译：半导体存储装置的接收器包括：第一输入晶体管，其配置为当输入信号等于或大于预定电平时导通; 配置为当输入信号等于或小于预定电平时导通的第二输入晶体管; 第一输出节点电压控制单元，被配置为当所述第一输入晶体管导通时增加输出节点的电压电平; 第二输出节点电压控制单元，被配置为当所述第二输入晶体管导通时降低所述输出节点的电压电平; 第三输入晶体管，被配置为当所述输入信号的反相信号等于或小于所述预定电压电平时，增加所述输出节点的电压电平; 以及第四输入晶体管，被配置为当输入信号的反相信号等于或大于预定电压电平时降低输出节点的电压电平。

97. 发明申请

US20110029700A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20110029700A1
公开(公告)日：2011-02-03
申请号：US12648524
申请日：2009-12-29
申请人： Ji Wang LEE , Hee Woong SONG , Tae Jin HWANG
发明人： Ji Wang LEE , Hee Woong SONG , Tae Jin HWANG
IPC分类号： G06F1/12
CPC分类号： G06F13/4072
摘要： A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.
摘要翻译：半导体装置包括时钟输入缓冲器，异步数据输入缓冲器和同步数据输入缓冲器。时钟输入缓冲器配置为缓冲外部时钟以产生内部时钟。异步数据输入缓冲器被配置为缓冲通过数据焊盘输入的数据并输出缓冲的数据。同步数据输入缓冲器被配置为与内部时钟同步以缓冲缓冲的数据。半导体装置被布置成使得用于将内部时钟传送到同步数据输入缓冲器的线的长度和用于将缓冲数据传送到同步数据输入缓冲器的线的长度基本上彼此相等。

98. 发明授权

US07863957B2 Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same 有权
标题翻译：占空比校正电路和包括其的半导体集成电路装置
公开(公告)号：US07863957B2
公开(公告)日：2011-01-04
申请号：US12331294
申请日：2008-12-09
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K5/151 , H03K2005/00058
摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.
摘要翻译：占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发，延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

99. 发明授权

US07825699B2 Receiver circuit having compensated offset voltage 失效
标题翻译：接收器电路具有补偿失调电压
公开(公告)号：US07825699B2
公开(公告)日：2010-11-02
申请号：US11822503
申请日：2007-07-06
申请人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Joon-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim
发明人： Tae-Jin Hwang , Kun-Woo Park , Yong-Ju Kim , Joon-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim
IPC分类号： G01R19/00 , G11C7/00 , H03F3/45
CPC分类号： H03F3/45766 , G11C7/02 , G11C7/065 , G11C7/08 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/109 , H03F3/45179 , H03F3/45475 , H03F3/45991 , H03F2203/45136 , H03F2203/45212 , H03F2203/45352 , H03F2203/45354
摘要： A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.
摘要翻译：接收器电路包括偏移控制信号生成单元，其使用偏移电压输出多个偏移控制信号。读出放大器分别接收基于上输入信号和下输入信号产生的第一电流和第二电流，将第一电流和第二电流分别转换成上补偿信号和具有补偿电位的下补偿信号偏移电压，并放大上补偿信号和下降补偿信号，以输出上输出信号和下输出信号。

100. 发明授权

US07795936B2 Data center tracking circuit and semiconductor integrated circuit including the same 有权
标题翻译：数据中心跟踪电路和半导体集成电路包括相同
公开(公告)号：US07795936B2
公开(公告)日：2010-09-14
申请号：US12174579
申请日：2008-07-16
申请人： Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Yong-Ju Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/093 , H04L7/033
摘要： A data center tracking circuit includes a clock tree, a sensing block, and a delay compensation block. The clock tree includes a plurality of clock buffers connected in series, buffers a clock, and outputs an output signal. The sensing block senses the phase change of the output signal on the basis of the clock, and outputs a sensing signal. The delay compensation block adjusts current to be supplied to the clock tree in response to the sensing signal, and adjusts the phase of the output signal.
摘要翻译：数据中心跟踪电路包括时钟树，感测块和延迟补偿块。时钟树包括串联连接的多个时钟缓冲器，缓冲时钟，并输出输出信号。感测块基于时钟感测输出信号的相位变化，并输出感测信号。延迟补偿块响应于感测信号调整提供给时钟树的电流，并调整输出信号的相位。

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