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1. 发明授权

US08144530B2 Semiconductor memory device and method for generating output enable signal 有权
标题翻译：半导体存储器件和产生输出使能信号的方法
公开(公告)号：US08144530B2
公开(公告)日：2012-03-27
申请号：US12494403
申请日：2009-06-30
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： H03L7/0816 , G11C7/1066 , G11C7/222 , H03L7/0805
摘要： A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal.
摘要翻译：半导体存储器件能够响应于读取命令和CAS延迟信息而产生输出使能信号。半导体存储器件包括：延迟锁定环，被配置为检测外部时钟信号和反馈时钟信号的相位差，产生对应于检测到的相位差的延迟控制信号，并通过延迟外部时钟信号产生DLL时钟信号延迟一段时间对应于延迟控制信号，延迟配置为响应于延迟控制信号而输出有效信号作为输出使能复位信号;以及输出使能信号发生器，其被配置为响应于输出使能复位信号复位;以及通过对外部时钟信号和DLL时钟信号进行计数，响应于读取信号和CAS等待时间信号产生输出使能信号。

2. 发明授权

US08143940B2 Internal supply voltage generating circuit and method for generating internal supply voltage 失效
标题翻译：内部电源电压发生电路及产生内部电源电压的方法
公开(公告)号：US08143940B2
公开(公告)日：2012-03-27
申请号：US12347605
申请日：2008-12-31
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/56 , G11C5/145 , H03L7/0812 , H03L7/093
摘要： An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
摘要翻译：内部电源电压产生电路包括：时钟比较器，被配置为将具有与参考电压电平相对应的时钟信息的第一时钟信号与具有对应于内部电源电压电平的时钟信息的第二时钟信号进行比较;控制信号发生器被配置为产生具有与所述时钟比较器的输出信号相对应的电压电平的驱动控制电压; 以及配置为响应于驱动控制电压驱动内部电源电压的端子的驱动器。

3. 发明授权

US07952364B2 Power noise detecting device and power noise control device using the same 失效
标题翻译：功率噪声检测装置和功率噪声控制装置使用相同
公开(公告)号：US07952364B2
公开(公告)日：2011-05-31
申请号：US12332294
申请日：2008-12-10
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G01R29/26
CPC分类号： H03H1/0007 , H03K19/00346
摘要： A power noise detecting device includes a plurality of power lines, and a power noise detecting part configured to detect power noise by rectifying voltages of the plurality of power lines and converting the rectified voltages into effective voltages.
摘要翻译：电力噪声检测装置包括多个电力线，以及电力噪声检测部，被配置为通过整流多个电力线的电压并将整流电压转换为有效电压来检测电力噪声。

4. 发明授权

US07936620B2 Receiver of semiconductor memory apparatus 有权
标题翻译：半导体存储器的接收器
公开(公告)号：US07936620B2
公开(公告)日：2011-05-03
申请号：US12483413
申请日：2009-06-12
申请人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Tae-Jin Hwang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1084
摘要： A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.
摘要翻译：半导体存储装置的接收器包括：第一输入晶体管，其配置为当输入信号等于或大于预定电平时导通; 配置为当输入信号等于或小于预定电平时导通的第二输入晶体管; 第一输出节点电压控制单元，被配置为当所述第一输入晶体管导通时增加输出节点的电压电平; 第二输出节点电压控制单元，被配置为当所述第二输入晶体管导通时降低所述输出节点的电压电平; 第三输入晶体管，被配置为当所述输入信号的反相信号等于或小于所述预定电压电平时，增加所述输出节点的电压电平; 以及第四输入晶体管，被配置为当输入信号的反相信号等于或大于预定电压电平时降低输出节点的电压电平。

5. 发明授权

US07863957B2 Duty cycle correction circuit and semiconductor integrated circuit apparatus including the same 有权
标题翻译：占空比校正电路和包括其的半导体集成电路装置
公开(公告)号：US07863957B2
公开(公告)日：2011-01-04
申请号：US12331294
申请日：2008-12-09
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K5/04
CPC分类号： H03K5/1565 , H03K5/151 , H03K2005/00058
摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.
摘要翻译：占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发，延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

6. 发明授权

US08339159B2 Input buffer circuit of semiconductor apparatus 有权
标题翻译：半导体装置的输入缓冲电路
公开(公告)号：US08339159B2
公开(公告)日：2012-12-25
申请号：US12540496
申请日：2009-08-13
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K5/153
CPC分类号： H03K5/153
摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
摘要翻译：半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

7. 发明授权

US08026701B2 Voltage regulator for a synchronous clock system to reduce clock tree jitter 失效
标题翻译：用于同步时钟系统的电压调节器，以减少时钟树抖动
公开(公告)号：US08026701B2
公开(公告)日：2011-09-27
申请号：US12265908
申请日：2008-11-06
申请人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Hyung-Soo Kim , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G05F1/652
CPC分类号： G11C5/147
摘要： A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.
摘要翻译：具有自适应带宽的电压调节器，包括第一缓冲链，电压产生单元，微调电容器单元，第二缓冲链和控制单元。第一个缓冲链使用外部电压作为电源电压来延迟时钟信号。电压产生单元基于参考电压产生调节电压。微调电容器单元控制电压产生单元的负载电容。第二缓冲链使用调节电压作为电源电压来延迟时钟信号。控制单元通过检测从第一和第二缓冲器链输出的时钟的延迟差来调节负载电容。

8. 发明授权

US07884659B2 Phase mixer and delay locked loop including the same 有权
标题翻译：相位混合器和延迟锁定环包括相同
公开(公告)号：US07884659B2
公开(公告)日：2011-02-08
申请号：US12347298
申请日：2008-12-31
申请人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
发明人： Jae-Min Jang , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Chang-Kun Park
IPC分类号： H03K11/16
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03L7/0818
摘要： A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.
摘要翻译：相位混合器包括：相位混合单元，被配置为响应于相位控制信号混合第一输入信号的相位和第二输入信号的相位，并输出相位混合信号，该相位混合信号的相位由一个或多个单位单位相位值，以及相位值调整单元，被配置为控制短语混合单元的操作，使得响应于代码信号来编码单位相位值，编码信号编码处理，电压或温度（PVT）变化中的至少一个。

9. 发明授权

US07868667B2 Output driving device 失效
标题翻译：输出驱动装置
公开(公告)号：US07868667B2
公开(公告)日：2011-01-11
申请号：US12411893
申请日：2009-03-26
申请人： Chang-Kun Park , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
发明人： Chang-Kun Park , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang
IPC分类号： H03K3/00
CPC分类号： H03K19/0027 , H03K19/00323 , H03K2005/00123 , H03K2217/0018
摘要： An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit.
摘要翻译：提供了能够提高转换速度的输出驱动装置。输出驱动装置包括配置有上拉PMOS晶体管和下拉式NMOS晶体管的推挽型驱动单元，其中上拉PMOS晶体管和下拉式NMOS晶体管的体偏置被控制以控制驱动单元的输出信号的转换速率。

10. 发明授权

US07847592B2 Buffer circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储装置的缓冲电路
公开(公告)号：US07847592B2
公开(公告)日：2010-12-07
申请号：US12494757
申请日：2009-06-30
申请人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
发明人： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018521
摘要： A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level.
摘要翻译：半导体存储装置的缓冲电路包括：缓冲部，被配置为通过将输入信号的电压电平与参考电压的电压电平进行比较来增大或减小输出节点的电压电平。当参考电压的电平低于目标电平时，电压补偿部分与输出节点成比例地与参考电压的变化成比例。

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