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91. 发明授权

US06897799B1 Current parking return to zero digital-to-analog converter 有权
标题翻译：当前停车返回到零数模转换器
公开(公告)号：US06897799B1
公开(公告)日：2005-05-24
申请号：US10897240
申请日：2004-07-22
申请人： Harry S. Harberts , Jeffrey M. Hinrichs
发明人： Harry S. Harberts , Jeffrey M. Hinrichs
IPC分类号： H03K17/041 , H03K17/16 , H03M1/06 , H03M1/74 , H03M3/00 , H03M3/02 , H03M1/66
CPC分类号： H03M1/06 , H03K17/04113 , H03K17/16 , H03M1/742 , H03M3/348 , H03M3/502
摘要： A digital-to-analog converter having a differential signal path, and a current parking circuit that is independent of the signal path, thereby avoiding a source of imbalance that caused output anomalies in conventional digital-to-analog circuitry. In one embodiment of the invention, a pair of diodes in the current parking circuit are connected through their own independent load resistors to a voltage source. In another embodiment, a single diode is used instead of the pair of diodes, and in a third embodiment the current parking circuit comprises a single load resistor connected to the voltage source, and no diodes at all.
摘要翻译：具有差分信号路径的数模转换器和独立于信号路径的当前停车电路，从而避免在常规数模转换电路中引起输出异常的不平衡源。在本发明的一个实施例中，当前停车电路中的一对二极管通过它们自己的独立负载电阻器连接到电压源。在另一个实施例中，使用单个二极管代替一对二极管，并且在第三实施例中，当前的停车电路包括连接到电压源的单个负载电阻器，并且根本不存在二极管。

92. 发明申请

US20050104759A1 Digital to analogue converter description 审中-公开
标题翻译：数模转换器描述
公开(公告)号：US20050104759A1
公开(公告)日：2005-05-19
申请号：US10498759
申请日：2002-12-06
申请人： Adrianus Van Tuijl
发明人： Adrianus Van Tuijl
IPC分类号： H03M1/08 , H03M1/06 , H03M1/74 , H03M1/78 , H03M1/66
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/464
摘要： A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1, 40-2, 40-n) are used may be changed in different samples. The current sources (40-1, 40-2, 40-n) may be replaced by one bit switched capacitor converters or by inverters connected to one end of a set of resistors, the other ends of which are connected to the virtual ground for an operational amplifier or alternatively to each other and arranged to directly generate the output voltage. According to one embodiment of the invention there is provided a sigma-delta analogue to digital converter comprising the circuit of the first aspect. A method is also provided which can be done by controlling each source with a duty cycle of M/2n, where n is the required resolution of the converter and M is the input word, and controlling different sources with a time shift. This allows an equal contribution from all the elements in one sample period with reduced switching and low sensitivity for time jitter.
摘要翻译：一种用于模数转换或数模转换的电路，包括至少2n匹配电流源（40-1,40-2,40-n），其中n是转换所需的分辨率。优选地，使用多于2n个电流源（40-1,40-2,40-n）。使用源（40 - 1，40 - 2，40 -n）的顺序可以在不同的样本中改变。电流源（40-1,40-2,40-n）可以由一位开关电容器转换器或连接到一组电阻器的一端的反相器代替，其另一端连接到虚拟地运算放大器或彼此交替并被布置成直接产生输出电压。根据本发明的一个实施例，提供了包括第一方面的电路的Σ-Δ模数转换器。还提供了一种可以通过以M / 2n的占空比控制每个源来完成的方法，其中n是转换器的所需分辨率，M是输入字，并且用时间偏移来控制不同的源。这允许在一个采样周期中所有元件的等效贡献，具有降低的开关和低灵敏度的时间抖动。

93. 发明授权

US06891488B1 Sigma-delta conversion with analog, nonvolatile trimmed quantized feedback 失效
标题翻译：具有模拟，非易失性微调量化反馈的Sigma-delta转换
公开(公告)号：US06891488B1
公开(公告)日：2005-05-10
申请号：US10696946
申请日：2003-10-30
申请人： Bart R. McDaniel , Malcolm H. Smith
发明人： Bart R. McDaniel , Malcolm H. Smith
IPC分类号： H03M1/10 , H03M1/74 , H03M3/04 , H03M3/00
CPC分类号： H03M1/1057 , H03M1/742 , H03M3/424 , H03M3/45 , H03M3/454
摘要： An Nth-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.
摘要翻译：具有多电平量化反馈的第N个Σ-Δ模数转换器（ADC）系统。多电平量化反馈级采用多位电流模式数模转换器（DAC）。在一个实施例中，用于DAC的参考电流源可以包括多个浮栅MOS晶体管，使得可以实现反馈DAC的模拟非易失性精度线性修整。 DAC的校准可以以相对低的刷新速率执行，例如仅在Σ-ΔADC系统被激活的情况下执行。

94. 发明授权

US06853014B2 Optoelectronic circuit employing a heterojunction thyristor device that performs high speed sampling 有权
标题翻译：采用进行高速采样的异质结晶闸管器件的光电子电路
公开(公告)号：US06853014B2
公开(公告)日：2005-02-08
申请号：US10323390
申请日：2002-12-19
申请人： Geoff W. Taylor , Jianhong Cai
发明人： Geoff W. Taylor , Jianhong Cai
IPC分类号： H01L21/331 , H01L21/335 , H01L29/15 , H01L29/80 , H03K17/79 , H03M1/66 , H03M1/74 , H03M1/80 , H01L31/072
CPC分类号： H01L29/155 , H01L29/66318 , H01L29/66462 , H01L29/802 , H01L31/1113 , H03K17/79 , H03M1/667 , H03M1/74 , H03M1/808
摘要： An optoelectronic circuit employing a heterojunction thyristor device that is configured as an optically-controlled (or electrically-controlled) sampling/switching device. First and second channel regions are disposed between the anode terminal and the cathode terminal of the device, and an electrical input terminal and an electrical output terminal are coupled to opposite ends of the first channel region. At least one control signal is supplied to the device. When the control signal corresponds to a predetermined ON condition, sufficient charge is stored in the second channel region to cause the heterojunction thyristor device to operate in an ON state whereby current flows between the anode terminal and the cathode terminal and the electrical input terminal is electrically coupled to the electrical output terminal. When the control signal corresponds to a predetermined OFF condition, the heterojunction thyristor device operates in an OFF state whereby current does not flow between the anode terminal and the cathode terminal and the electrical input terminal is electrically isolated from the electrical output terminal. The control signal can be an optical sampling clock, a digital optical signal encoding bits of information, the combination of a digital optical signal and an optical sampling clock (which defines sampling periods that overlap the bits of information in the digital optical signal), or an electrical sampling clock.
摘要翻译：采用被配置为光控（或电控））采样/切换装置的异质结晶闸管器件的光电子电路。第一和第二通道区域设置在器件的阳极端子和阴极端子之间，并且电输入端子和电输出端子耦合到第一通道区域的相对端。至少一个控制信号被提供给设备。当控制信号对应于预定的ON状态时，在第二通道区域中存储足够的电荷，使得异质结晶闸管器件工作在导通状态，由此电流在阳极端子和阴极端子之间流动，并且电输入端子电耦合到电输出端子。当控制信号对应于预定的OFF状态时，异质结晶闸管器件工作在OFF状态，由此电流不在阳极端子和阴极端子之间流动，并且电气输入端子与电气输出端子电隔离。控制信号可以是光采样时钟，编码信息位的数字光信号，数字光信号和光采样时钟（其定义与数字光信号中的信息位重叠的采样周期）的组合，或电采样时钟。

95. 发明授权

US06844835B2 DAC cell circuit 有权
标题翻译： DAC单元电路
公开(公告)号：US06844835B2
公开(公告)日：2005-01-18
申请号：US10609569
申请日：2003-07-01
申请人： Hsueh-Wu Kao
发明人： Hsueh-Wu Kao
IPC分类号： H03M1/06 , H03M1/08 , H03M1/74 , H03M1/66
CPC分类号： H03M1/0678 , H03M1/0863 , H03M1/742
摘要： A digital-analog converter (DAC) cell circuit. The circuit includes a current source, a first resistor, a second resistor, a first MOSFET, a second MOSFET, a third MOSFET and a forth MOSFET. The first MOSFET has a source and a drain connected to the current source and the first resistor, respectively, and a gate receiving a first control signal. The second MOSFET has a source and a drain connected to the current source and the second resistor, respectively, and a gate receiving a second control signal. The third MOSFET has a source and a drain connected to the source and drain of the first MOSFET, respectively, and a gate receiving a third control signal. The fourth MOSFET has a source and a drain connected to the source and drain of the second MOSFET, respectively, and a gate receiving a fourth control signal. The third control signal is a signal delayed of the first signal and the forth control signal is a signal delayed of the second signal. The delayed control signal can be used to control the slew rate of current DAC cell, thus reduce the package inductance induced L di/dt noise. Also it can be used to reduce the voltage fluctuations during current switching so as to get fast settling current.
摘要翻译：数模转换器（DAC）单元电路。电路包括电流源，第一电阻器，第二电阻器，第一MOSFET，第二MOSFET，第三MOSFET和第四MOSFET。第一MOSFET具有分别连接到电流源和第一电阻的源极和漏极，以及接收第一控制信号的栅极。第二MOSFET分别具有连接到电流源和第二电阻的源极和漏极，以及接收第二控制信号的栅极。第三MOSFET分别具有连接到第一MOSFET的源极和漏极的源极和漏极，以及接收第三控制信号的栅极。第四MOSFET分别具有连接到第二MOSFET的源极和漏极的源极和漏极，以及接收第四个控制信号的栅极。第三控制信号是延迟第一信号的信号，第四控制信号是延迟第二信号的信号。延迟控制信号可用于控制电流DAC单元的转换速率，从而降低封装电感引起的L di / dt噪声。此外，它可以用于降低电流开关期间的电压波动，以获得快速的稳定电流。

96. 发明授权

US06842132B2 Constant switching for signal processing 有权
标题翻译：信号处理恒定切换
公开(公告)号：US06842132B2
公开(公告)日：2005-01-11
申请号：US10351470
申请日：2003-01-24
申请人： Bernd Schafferer
发明人： Bernd Schafferer
IPC分类号： H03M1/06 , H03M1/74 , H03M1/00 , H03M1/66
CPC分类号： H03M1/068 , H03M1/742
摘要： Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.
摘要翻译：描述了诸如数模转换器（DAC）的信号处理电路中用于代码独立切换的方法和装置，其提供与代码无关的切换活动。转向单元接收以数据间隔定义的数字数据输入信号，并产生多个代表性的模拟输出信号。对于每个数据间隔，每个模拟输出信号仅取决于数字数据输入信号的当前状态，独立于数字数据输入信号的任何先前状态。此外，除了模拟输出信号之外的信号处理电路基本上没有数据相关的干扰。

97. 发明授权

US06163283A Thermometer coding circuitry 有权
标题翻译：温度计编码电路
公开(公告)号：US06163283A
公开(公告)日：2000-12-19
申请号：US227200
申请日：1999-01-08
申请人： William George John Schofield
发明人： William George John Schofield
IPC分类号： H03M1/74 , H03M1/68 , H03M7/16 , H03M1/00 , H03M1/66 , H03M1/80 , H03M7/00
CPC分类号： H03M1/685 , H03M1/747 , H03M7/165
摘要： Coding circuitry (34), for use for example in selecting cells of a cell array in a digital-to-analog converter, produces first and second sets of thermometer-coded output signals in dependence upon a binary input signal. As the input signal increases progressively in value from a first value to a second value, the first-set output signals (COLA) are activated in a predetermined sequence and the second-set output signals (COLB) are deactivated in a predetermined sequence. As the input signal increases progressively in value from the second value to a third value, the first-set output signals are deactivated in a predetermined sequence and the second-set output signals are activated in a predetermined sequence.Such coding circuitry reduces the numbers of output signals that change in response to changes in the input-signal value.In another embodiment (FIG. 12) the coding circuitry includes respective row, column and depth decoders (58, 56, 54). The row decoder receives the two most significant bits S4 and S5 of a binary input word and derives therefrom a set of thermometer-coded row selection signals (ROW0-2). The column decoder receives the two middle-order bits S2 and S3 of the binary input word and derives therefrom at least one set of thermometer-coded column selection signals (COLA0-2,COLB0-2). The depth decoder receives the two least-significant bits S0 and S1 of the binary input word and derives therefrom at least one set of thermometer-coded depth selection signals (DEPA0-2,DEPB0-2).Such coding circuitry can enable selection of elements from amongst a large array of elements using only a small number of thermometer-coded signals.
摘要翻译：用于例如在数模转换器中选择单元阵列的单元的编码电路（34）根据二进制输入信号产生第一组和第二组温度计编码的输出信号。随着输入信号从第一值逐渐增加到第二值，第一组输出信号（COLA）以预定的顺序被激活，并且第二组输出信号（COLB）以预定的顺序被去激活。当输入信号从第二值逐渐增加到第三值时，第一组输出信号以预定的顺序被去激活，并且第二组输出信号以预定的顺序被激活。这种编码电路减少了响应于输入信号值的变化而改变的输出信号的数量。在另一实施例（图12）中，编码电路包括相应的行，列和深度解码器（58,56,54）。行解码器接收二进制输入字的两个最高有效位S4和S5，并从其中导出一组温度计编码的行选择信号（ROW0-2）。列解码器接收二进制输入字的两个中间位S2和S3，并从其中导出至少一组温度计编码列选择信号（COLA0-2，COLB0-2）。深度解码器接收二进制输入字的两个最低有效位S0和S1，并从其中导出至少一组温度计编码深度选择信号（DEPA0-2，DEPB0-2）。这种编码电路可以使用仅使用少量温度计编码的信号来从大量元件中选择元件。

98. 发明授权

US6154160A Circuit arrangement including digital-to-analog current converters 失效
标题翻译：电路布置包括数模转换电流
公开(公告)号：US6154160A
公开(公告)日：2000-11-28
申请号：US253085
申请日：1999-02-19
申请人： Robert Meyer , Othmar Pfarrkircher
发明人： Robert Meyer , Othmar Pfarrkircher
IPC分类号： H03M1/74 , H03M1/10 , H03M1/70 , H03M1/62
CPC分类号： H03M1/70 , H03M1/1014
摘要： A circuit checks the value and the existence of an external load of a digital-to-analog current converter. A first comparator compares a digital word to be converted, with a comparison data word. The output signal of the first converter indicates during which periods the digital data word is greater and during which periods it is smaller than the comparison data word. A second comparator compares the voltage at the output of the converter with a reference voltage. The output signal of the second converter indicates during which periods the output voltage is greater and during which periods it is smaller than the reference voltage. A comparison circuit checks the existence and the value of the output load by comparing the time periods indicated by the output signals of the two converters. Thus, a conclusion about the existence and the value of the output load is possible at any time.
摘要翻译：电路检查数字 - 模拟电流转换器的外部负载的值和存在。第一比较器将要转换的数字字与比较数据字进行比较。第一转换器的输出信号指示数字数据字在哪段期间较大，在该期间小于比较数据字。第二个比较器将转换器输出端的电压与参考电压进行比较。第二转换器的输出信号表示在哪个周期内输出电压较大，在该期间小于参考电压。比较电路通过比较由两个转换器的输出信号指示的时间段来检查输出负载的存在和值。因此，可以随时得出关于输出负载的存在和价值的结论。

99. 发明授权

US6154121A Non-linear digital-to-analog converter and display incorporating the same 有权
标题翻译：非线性数模转换器和包含其的显示器
公开(公告)号：US6154121A
公开(公告)日：2000-11-28
申请号：US229458
申请日：1999-01-12
申请人： Graham Andrew Cairns , Michael James Brownlow
发明人： Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G09G3/20 , G02F1/133 , H03M1/66 , H03M1/74 , H03K13/02 , H03M1/18
CPC分类号： H03M1/664
摘要： A non-linear digital-to-analog converter includes: a k bit parallel input; a decoding circuit having M inputs connected to M most significant bits of the parallel input, the decoding circuit being arranged to connect first and second consecutive reference inputs among 2.sup.m +1 reference inputs to first and second outputs, respectively, where M>m; and a variable resolution linear digital-to-analog converter having first and second reference inputs connected to the first and second outputs of the decoding circuit, respectively, and further having N digital inputs connected to N least significant bits of the parallel input, where (M+N)>k.
摘要翻译：非线性数模转换器包括：k位并行输入; M个输入连接到并行输入的M个最高有效位的解码电路，所述解码电路被配置为将2m + 1个参考输入中的第一和第二连续参考输入分别连接到第一和第二输出，其中M> m; 以及可变分辨率线性数模转换器，其具有分别连接到解码电路的第一和第二输出的第一和第二参考输入，并且还具有连接到并行输入的N个最低有效位的N个数字输入，其中（ M + N）> k。

100. 发明授权

US6130632A Digitally self-calibrating current-mode D/A converter 失效
标题翻译：数字自校准电流模式D / A转换器
公开(公告)号：US6130632A
公开(公告)日：2000-10-10
申请号：US62157
申请日：1998-04-16
申请人： Ion E. Opris
发明人： Ion E. Opris
IPC分类号： H03M1/10 , H03M1/74
CPC分类号： H03M1/1061 , H03M1/742
摘要： Digital self-calibration of digital-to-digital converters includes an approach to correct for the arbitrary errors in the analog section provided that there are sufficient redundancy in the architecture. The calibration procedure is performed off-line (upon power-up or user request). The digital correction technique avoids the need of a very accurate current mirror or an extra digital-to-analog converter as a standard transfer device.
摘要翻译：数字 - 数字转换器的数字自校准器包括一种纠正模拟部分任意错误的方法，前提是架构中有足够的冗余。校准程序离线执行（上电或用户请求时）。数字校正技术避免了使用非常精确的电流镜或额外的数模转换器作为标准传送装置。

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