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91. 发明授权

US6122336A Digital clock recovery circuit with phase interpolation 失效
标题翻译：数字时钟恢复电路，具有相位插值
公开(公告)号：US6122336A
公开(公告)日：2000-09-19
申请号：US927947
申请日：1997-09-11
申请人： Michael B. Anderson
发明人： Michael B. Anderson
IPC分类号： H03L7/07 , H03L7/081 , H03L7/099 , H04L7/033 , H04L25/40 , H03D3/24 , H04L7/00
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0996 , H04L7/0337
摘要： The present invention provides a digital clock recovery circuit, which includes a frequency synthesizer generating a number of clock phase signals. The digital clock recovery circuit also includes a phase interpolation unit, which interpolates the clock phase signals from the frequency synthesizer to increase the number of clock phase signals. Additionally, the digital clock recovery circuit also includes a phase detector, a digital filter, and a phase selection unit. The phase detector has an output connected to a digital filter, which is connected to the phase selection unit. The phase detector sends signals filtered through the digital filter to select clock phase signals input into the phase selection unit from the phase interpolation unit. The output of the phase selector provides the recovered clock signal and also connected to the input phase detector.
摘要翻译：本发明提供了一种数字时钟恢复电路，其包括产生多个时钟相位信号的频率合成器。数字时钟恢复电路还包括相位插值单元，其内插来自频率合成器的时钟相位信号以增加时钟相位信号的数量。此外，数字时钟恢复电路还包括相位检测器，数字滤波器和相位选择单元。相位检测器具有连接到数字滤波器的输出，该数字滤波器连接到相位选择单元。相位检测器发送通过数字滤波器滤波的信号，从相位插值单元中选择输入到相位选择单元的时钟相位信号。相位选择器的输出提供恢复的时钟信号，并连接到输入相位检测器。

92. 发明授权

US6118314A Circuit assembly and method of synchronizing plural circuits 失效
标题翻译：电路组件和多个电路同步的方法
公开(公告)号：US6118314A
公开(公告)日：2000-09-12
申请号：US173441
申请日：1998-10-14
申请人： Patrick Arnould , Frederic Hayem
发明人： Patrick Arnould , Frederic Hayem
IPC分类号： G06F1/10 , H03L7/07 , H04J3/06 , H03L7/00
CPC分类号： H04J3/0685 , G06F1/10 , H03L7/07
摘要： The present invention includes a circuit assembly and method of synchronizing plural circuits. According to one aspect of the present invention, a circuit includes: an oscillator configured to generate a reference clock signal; a first circuit including: a first divider configured to generate a first internal clock signal responsive to the reference clock signal; and reset generation circuitry configured to receive an external reset signal and generate a reset second circuit signal synchronized with a predefined position of the first divider, with the reference clock signal and with the external reset signal; and a second circuit including: reset detection circuitry configured to generate a reset detection signal synchronized with the reset second circuit signal and the reference clock signal; and a second divider configured to set to a predefined position responsive to the reception of the reset detection signal and generate a second internal clock signal synchronized with the first internal clock signal.
摘要翻译：本发明包括一种同步多个电路的电路组件和方法。根据本发明的一个方面，电路包括：被配置为产生参考时钟信号的振荡器; 第一电路包括：第一分配器，被配置为响应于参考时钟信号产生第一内部时钟信号; 以及复位产生电路，其被配置为接收外部复位信号并产生与所述第一分频器的预定义位置同步的复位第二电路信号与所述参考时钟信号和所述外部复位信号; 以及第二电路，包括：复位检测电路，被配置为产生与所述复位第二电路信号和所述参考时钟信号同步的复位检测信号; 以及第二分频器，被配置为响应于所述复位检测信号的接收而设置到预定位置，并且产生与所述第一内部时钟信号同步的第二内部时钟信号。

93. 发明授权

US6104250A Method and an apparatus for controlling an oscillator for generating a linear frequency sweep by use of a phase-locked loop 有权
标题翻译：用于通过使用锁相环来控制用于产生线性频率扫描的振荡器的方法和装置
公开(公告)号：US6104250A
公开(公告)日：2000-08-15
申请号：US214005
申请日：1998-12-24
申请人： Christer Eckersten , Joakim Olofsson
发明人： Christer Eckersten , Joakim Olofsson
IPC分类号： H03L7/12 , G01S7/02 , G01S7/282 , G01S7/35 , G01S13/34 , H03B23/00 , H03L7/07 , H03L7/22 , H03L7/23 , H04B1/26 , H03J7/18 , H03L7/18
CPC分类号： H03B23/00 , G01S13/34 , G01S7/282 , H03L7/23 , G01S7/352 , H03B2200/0092
摘要： A method and an apparatus for controlling a radar oscillator for use in the traffic field, in particular for a car radar, for generating a linear frequency sweep. A phase-locked linearization loop generates a linear frequency sweep controlling a phase-locked oscillator loop, which has a considerably broader bandwidth than the linearization loop.
摘要翻译： PCT No.PCT / SE97 / 01178 Sec。一九九九年二月二十二日 102（e）1999年2月22日PCT 1997年6月30日PCT公布。第WO98 / 00920号公报日期1998年1月8日一种用于控制在业务领域（特别是汽车雷达）中用于生成线性频率扫描的雷达振荡器的方法和装置。锁相线性化环路产生线性频率扫描，控制锁相振荡器环路，其具有比线性化环路宽得多的带宽。

94. 发明授权

US6104228A Phase aligner system and method 失效
标题翻译：相位对准系统和方法
公开(公告)号：US6104228A
公开(公告)日：2000-08-15
申请号：US997084
申请日：1997-12-23
申请人： Kadaba R. Lakshmikumar
发明人： Kadaba R. Lakshmikumar
IPC分类号： H03K5/135 , H03L7/07 , H03L7/081 , H04L7/00 , H04L7/033 , H03K17/62 , H03H11/26
CPC分类号： H03K5/135 , H03L7/07 , H03L7/0814 , H04L7/0083 , H04L7/0337
摘要： A system for aligning the phase of signals generated by a selectable standby clock source which has a predetermined frequency with the phase of signals generated by a selected clock source which has the same frequency as signals generated by the standby clock source. The system comprises (1) a delay line having a plurality of delay elements which is configured to receive the signals generated by the standby clock source so that the output signal of each delay element is a delayed version of the standby clock source; (2) a decoder configured to receive each of the delayed versions of the signals generated by the standby clock signal source and generates a selection signal corresponding to a desired one of the delayed version signals that is aligned with signals generated by the selected clock source within a specifiable phase difference; and (3) a selector configured to receive the selection signal so as to select the desired delayed version signal as a new standby clock source.
摘要翻译：一种用于将具有预定频率的可选待机时钟源产生的信号的相位与由选择的时钟源产生的信号的相位对准的系统，该选择时钟源具有与备用时钟源产生的信号相同的频率。该系统包括（1）具有多个延迟元件的延迟线，其被配置为接收由备用时钟源产生的信号，使得每个延迟元件的输出信号是备用时钟源的延迟版本; （2）解码器，其被配置为接收由备用时钟信号源产生的信号的每个延迟版本，并且生成对应于与所选择的时钟源所生成的信号对准的延迟版本信号中期望的一个的选择信号，一个可指定的相位差; 以及（3）选择器，被配置为接收选择信号，以便选择所需的延迟版本信号作为新的备用时钟源。

95. 发明授权

US6100735A Segmented dual delay-locked loop for precise variable-phase clock generation 失效
标题翻译：分段双延迟锁定环，用于精确的可变相位时钟生成
公开(公告)号：US6100735A
公开(公告)日：2000-08-08
申请号：US197320
申请日：1998-11-19
申请人： Crist Y. Lu
发明人： Crist Y. Lu
IPC分类号： H03L7/07 , H03L7/081 , H03L7/089 , H03L7/06
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/0891 , Y10S331/02
摘要： A segmented dual delay-locked-loop (DLL) has a coarse DLL and a fine DLL. Each DLL has a series of buffers, a phase detector, charge pump, and bias-voltage generator. The bias voltage controls the delay through the buffers. The bias voltage of the coarse DLL is adjusted by the phase comparator to lock the total delay through the buffers to be equal the input-clock period. The coarse DLL divides an input clock into M equal intervals of the input-clock period and generates M intermediate clocks having M different phases. An intermediate mux selects one of the M intermediate clocks in response to a phase-selecting address. The selected intermediate clock K and a next-following intermediate clock K+1 are both selected and applied to the fine DLL. The K clock is input to a series of N buffers in the fine DLL while the K+1 clock is directly input to a phase detector. The phase detector compares the K+1 clock to the K clock after the delay through the buffers. The bias voltage of the fine DLL is adjusted by the phase comparator to lock the total delay through the N buffers to the coarse interval between the K and K+1 intermediate clocks. Thus the input clock is divided into M intervals by the coarse DLL, then the fine DLL further divides one coarse interval into N intervals. Very fine phases are generated with only a M-buffer DLL and an N-buffer DLL.
摘要翻译：分段双延迟锁定环（DLL）具有粗略的DLL和精细的DLL。每个DLL都有一系列缓冲器，相位检测器，电荷泵和偏置电压发生器。偏置电压控制缓冲器的延迟。粗略DLL的偏置电压由相位比较器调整，以将通过缓冲器的总延迟锁定为等于输入时钟周期。粗略的DLL将输入时钟分为输入时钟周期的M个相等的间隔，并产生具有M个不同相位的M个中间时钟。中间多路复用器响应于相位选择地址选择M个中间时钟之一。所选择的中间时钟K和下一个跟随中间时钟K + 1都被选择并应用于精细DLL。 K时钟输入到精细DLL中的一系列N个缓冲器，而K + 1时钟直接输入到相位检测器。相位检测器通过缓冲器将延迟后的K + 1时钟与K时钟进行比较。通过相位比较器调整精细DLL的偏置电压，将通过N个缓冲器的总延迟锁定到K和K + 1个中间时钟之间的粗略间隔。因此，通过粗略的DLL将输入时钟分成M个间隔，则精细的DLL进一步将一个粗略的间隔划分成N个间隔。只有M缓冲区DLL和N缓冲区DLL才能生成非常精细的相位。

96. 发明授权

US6064869A Suppression of noise between phase lock loops in a selective call receiver and method therefor 失效
标题翻译：选择呼叫接收机中锁相环之间的噪声抑制及其方法
公开(公告)号：US6064869A
公开(公告)日：2000-05-16
申请号：US33011
申请日：1998-03-02
申请人： Darrell Eugene Davis , Scott Robert Humphreys
发明人： Darrell Eugene Davis , Scott Robert Humphreys
IPC分类号： H03L7/07 , H03L7/23 , H04B15/04 , H04Q7/30
CPC分类号： H03L7/07 , H03L7/23 , H04B15/04 , H04B2215/064
摘要： A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.
摘要翻译：合成器（100）用于产生多个合成时钟信号（128,156）。合成器包括用于产生公共频率参考信号（103）的时钟源（102）和耦合到公共频率参考信号的时钟发生器（104），用于产生多个产生的时钟信号（106,108），其中每个多个生成的时钟信号彼此偏移了预定的相位偏移（189,192）。另外，合成器包括多个PLL（锁相环）（166-168），用于产生多个合成时钟信号中选择的一个，其中多个PLL中的每一个耦合到相应的多个生成的时钟信号中的一个，并且其中已知多个所生成的时钟信号中的每一个之间的预定相位偏移，以抑制从其操作的多个PLL之间的噪声。

97. 发明授权

US6052011A Fractional period delay circuit 失效
标题翻译：分数周期延迟电路
公开(公告)号：US6052011A
公开(公告)日：2000-04-18
申请号：US966736
申请日：1997-11-10
申请人： Uday Dasgupta
发明人： Uday Dasgupta
IPC分类号： H03H11/26 , H03L7/07 , H03L7/081 , H03L7/093
CPC分类号： H03L7/0812 , H03H11/265 , H03L7/07 , H03L7/093
摘要： A fractional period delay circuit to delay a clocking signal by a non-integer fraction of the period of the clocking signal is disclosed. The fractional period delay circuit has a first delay line connected to a master timing signal to delay the master clock to form the first timing signal. The fractional period delay circuit has plurality of adjustable delay lines. Each adjustable delay line is connected to the master timing signal to delay the master timing A delay adjustment input will modify the delay of the adjustable delay circuit. The fractional period delay circuit further has a plurality of phase difference detectors connected to the output of the first delay line and to the output of one of the plurality of adjustable delay lines. The phase difference detector will create a difference signal indicating a difference in phase between the first timing signal and one of the delayed timing signals. A plurality of sequence timing signals are created in a is timing sequence generator. A phase correction calculators is connected to a phase difference detector and the timing sequence generator to calculate a delay adjustment signal. The delay adjustment signal is an error signal indicating the delay between the delayed timing signal and the first timing signal. The delay adjustment signal is transferred to a delay line adjustment circuit to adjust the delay of the adjustable delay line.
摘要翻译：公开了一种将时钟信号延迟时钟信号周期的非整数分数的分数周期延迟电路。分数周期延迟电路具有连接到主定时信号的第一延迟线，以延迟主时钟以形成第一定时信号。分数周期延迟电路具有多个可调延迟线。每个可调延迟线连接到主定时信号以延迟主机定时A延迟调整输入将修改可调延迟电路的延迟。分数周期延迟电路还具有连接到第一延迟线的输出和多个可调延迟线中的一个的输出的多个相位差检测器。相位差检测器将产生指示第一定时信号和延迟定时信号之一的相位差的差分信号。在一个定时序列发生器中产生多个序列定时信号。相位校正计算器连接到相位差检测器和定时序列发生器以计算延迟调整信号。延迟调整信号是指示延迟定时信号和第一定时信号之间的延迟的误差信号。延迟调整信号被传送到延迟线调整电路，以调整可调延迟线的延迟。

98. 发明授权

US6020773A Clock signal generator for generating a plurality of clock signals with different phases, and clock phase controller using the same 失效
标题翻译：用于产生具有不同相位的多个时钟信号的时钟信号发生器，以及使用其的时钟相位控制器
公开(公告)号：US6020773A
公开(公告)日：2000-02-01
申请号：US069312
申请日：1998-04-29
申请人： Yasuhiro Kan , Masaharu Taniguti
发明人： Yasuhiro Kan , Masaharu Taniguti
IPC分类号： H03K5/13 , H03K5/135 , H03K5/15 , H03L7/07 , H03L7/081 , H03L7/093 , H03H11/26
CPC分类号： H03L7/0805 , H03K5/13 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0812
摘要： A clock signal generator having a pre-phase converter for generating in response to an input clock signal a plurality of pre-delay clock signals with different phases; and main phase converters each of which receives one of the pre-delay clock signals, and generates a plurality of main delay clock signals with their phases different from each other, thereby generating multiple main delay clock signals with their phases different from each other.
摘要翻译：一种时钟信号发生器，具有用于响应于输入时钟信号产生具有不同相位的多个预延迟时钟信号的预相位转换器; 主相转换器中的每一个接收预延迟时钟信号之一，并且产生彼此相位不同的多个主延迟时钟信号，从而产生彼此相位不同的多个主延迟时钟信号。

99. 发明授权

US5982836A Phase synchronizer and data reproducing apparatus 失效
标题翻译：相位同步器和数据再现装置
公开(公告)号：US5982836A
公开(公告)日：1999-11-09
申请号：US831948
申请日：1997-04-02
申请人： Keisuke Sakae , Kimio Yoshikawa
发明人： Keisuke Sakae , Kimio Yoshikawa
IPC分类号： H03L7/087 , G11B20/14 , H03K3/03 , H03K23/66 , H03L7/07 , H03L7/099 , H03L7/10 , H03L7/113 , H03L7/14 , H03L7/183 , H03D3/24
CPC分类号： H03L7/0805 , G11B20/1403 , H03K23/665 , H03K3/03 , H03L7/07 , H03L7/0995 , H03L7/0997 , H03L7/10 , H03L7/148 , H03L7/183 , H03L2207/06
摘要： A phase synchronizer is disclosed that provides a stable output signal while improving synchronization speed. The phase synchronizer includes one or two feedback circuits. The feedback circuit(s) includes a phase comparator for generating a pulse signal in accordance with a difference between the phases of an input signal and a feedback signal, a charge pump for converting the pulse signal supplied from the phase comparator to an analog voltage signal, a loop filter for removing high-frequency signal components from the analog voltage signal output from the charge pump and supplying as a filtered analog voltage signal (LF1 or LF2), and a voltage-controlled oscillator coupled to the loop filter for generating an oscillation output signal having a frequency which varies in accordance with the filtered analog signal (LF1 or LF2). The oscillation output signal is also supplied as the feedback signal to the phase comparator.
摘要翻译：公开了提供稳定输出信号同步提高同步速度的相位同步器。相位同步器包括一个或两个反馈电路。反馈电路包括：相位比较器，用于根据输入信号和反馈信号的相位之间的差产生脉冲信号;电荷泵，用于将从相位比较器提供的脉冲信号转换为模拟电压信号，用于从电荷泵输出的模拟电压信号中去除高频信号分量并作为滤波模拟电压信号（LF1或LF2）提供的环路滤波器，以及耦合到环路滤波器以产生振荡的压控振荡器输出信号具有根据滤波的模拟信号（LF1或LF2）而变化的频率。振荡输出信号也作为反馈信号提供给相位比较器。

100. 发明授权

US5982242A Circuit for synchronizing transmission local oscillating frequencies in digital microwave system 失效
标题翻译：用于在数字微波系统中同步传输本地振荡频率的电路
公开(公告)号：US5982242A
公开(公告)日：1999-11-09
申请号：US45655
申请日：1998-03-20
申请人： Min-Sik Jun , Soo-Bok Kim
发明人： Min-Sik Jun , Soo-Bok Kim
IPC分类号： H04B1/04 , H03L7/24 , H03B5/00 , H03L7/07
CPC分类号： H03L7/24
摘要： A circuit for synchronizing transmission local oscillating frequency in a co-channel microwave system, with more reliability, synchronizes horizontal and vertical polarization waves phase locked dielectric resonators which generate transmission local oscillating frequencies in a digital co-channel microwave system. The circuit includes a first reference signal oscillator for outputting a first reference signal; a second reference signal oscillator for outputting a second reference signal; a first divider for dividing the power of the first reference signal and outputting first and second divided powers; a second divider for dividing the power of the second reference signal and outputting first and second divided powers; a first radio frequency signal generator for detecting the output level of the second divided second reference signal and for outputting one of the first divided first reference signal or the second divided second reference signal as a first radio frequency signal for input to the vertical polarization waves locked dielectric resonator, depending upon the detected result; and a second radio frequency signal generator for detecting the output level of the second divided first reference signal and for outputting one of the first divided second reference signal or the second divided first reference signal as a second radio frequency signal for input to the horizontal polarization waves locked dielectric resonator, depending upon the detected result; the first reference signal oscillator, the first divider, and the first radio frequency signal generator being included in one module and the second reference signal oscillator, the second divider, and the second radio frequency signal generator being included in another module.
摘要翻译：用于在同频道微波系统中同步传输本地振荡频率的电路，具有更高的可靠性，同步在数字同频道微波系统中产生传输本地振荡频率的水平和垂直偏振波相位锁定介质谐振器。该电路包括用于输出第一参考信号的第一参考信号振荡器; 第二参考信号振荡器，用于输出第二参考信号; 用于分割第一参考信号的功率并输出第一和第二分频的第一分频器; 用于分割第二参考信号的功率并输出第一和第二分频的第二分频器; 第一射频信号发生器，用于检测第二划分的第二参考信号的输出电平，并输出第一划分的第一参考信号或第二划分的第二参考信号中的一个作为第一射频信号，以输入到锁定的垂直偏振波介质谐振器，取决于检测结果; 以及第二射频信号发生器，用于检测第二划分的第一参考信号的输出电平，并输出第一划分的第二参考信号或第二划分的第一参考信号之一作为第二射频信号，以输入到水平极化波取决于检测结果; 第一参考信号振荡器，第一分频器和第一射频信号发生器被包括在一个模块中，第二参考信号振荡器，第二分频器和第二射频信号发生器被包括在另一个模块中。

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