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11. 发明申请

US20120329223A1 SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120329223A1
公开(公告)日：2012-12-27
申请号：US13551240
申请日：2012-07-17
申请人： Toshiaki TAKESHITA
发明人： Toshiaki TAKESHITA
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/11565 , H01L29/42344 , H01L29/66833 , H01L29/792
摘要： In a semiconductor storage device a select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction.
摘要翻译：在半导体存储装置中，选择栅电极被设置成围绕第二杂质区域的环形，并且与字线电连接。第一控制栅电极在选择栅电极的外周侧被布置成环形，并且第二控制栅电极在选择栅电极的内周侧上布置成环形。对应于每行的一对第一和第二位线被放置在器件的存储单元上，第一位线电连接到沿着行方向相邻的第一杂质区之一，第二位线是电连接到沿着行方向相邻的第一杂质区域中的另一个。

12. 发明申请

US20120326907A1 D/A CONVERTER INCLUDING HIGHER-ORDER RESISTOR STRING 有权
标题翻译： D / A转换器，包括高级电阻器STRING
公开(公告)号：US20120326907A1
公开(公告)日：2012-12-27
申请号：US13602821
申请日：2012-09-04
申请人： Koji HIRAI
发明人： Koji HIRAI
IPC分类号： H03M1/78
CPC分类号： H03M1/682 , G09G3/3688 , H03M1/00 , H03M1/747 , H03M1/765 , H03M1/785
摘要： A resistor string digital-to-analog converter includes an input terminal receiving a digital input signal in digital code, an output terminal revealing an analog output signal in analog voltage, a first plurality of voltage-acquisition nodes including a first pair of nodes which is adjacent to each other, a first plurality of resistors being connected in series via the first plurality of voltage-acquisition nodes, a second pair of nodes revealing a pair of analog voltages, a high-order voltage-acquisition circuit providing conduction between a respective one of the first pair of nodes and a respective one of the second pair of nodes in accordance with the digital input signal, a low-order converter generating the analog output signal, which is obtained by interpolating one and the other of the pair of analog voltages in accordance with the digital input signal.
摘要翻译：一种电阻串数模转换器，包括以数字码接收数字输入信号的输入端，以模拟电压显示模拟输出信号的输出端，包括第一对节点的第一多个电压采集节点，彼此相邻的第一多个电阻器通过第一多个电压采集节点串联连接，第二对节点露出一对模拟电压，高阶电压采集电路提供相应的一个的第一对节点和第二对节点中的相应一个根据数字输入信号，产生模拟输出信号的低阶转换器，其通过内插一对模拟电压中的一个和另一个而获得按照数字输入信号。

13. 发明申请

US20110035092A1 ANALOG/DIGITAL CONVERSION CIRCUIT, SEMICONDUCTOR DEVICE, AND ELECTRIC POWER STEERING CONTROLLING UNIT 失效
标题翻译：模拟/数字转换电路，半导体器件和电力转向控制单元
公开(公告)号：US20110035092A1
公开(公告)日：2011-02-10
申请号：US12851835
申请日：2010-08-06
申请人： Naoya OTA
发明人： Naoya OTA
IPC分类号： G06F7/00 , H03M1/34 , B62D15/02
CPC分类号： B62D5/046 , B60R16/0231 , H03M1/1215
摘要： The present invention provides a method in which a counting source is provided in data after analog/digital conversion to lessen a load placed when new and old data after the conversion are compared to each other. A log function is prepared in an A/D conversion controlling circuit. The log function latches the output of a counter in a 12-bit digital/analog converter at the timing of outputting a pulse from a comparator to determine data written into a data register group. In the case where a setting item related to log output in an ADCR is set at 1, not only the output of the 12-bit digital/analog converter, but also the output of a timer counter of an MTU is latched as a log.
摘要翻译：本发明提供了一种方法，其中在模拟/数字转换之后的数据中提供计数源，以减少在转换之后的新旧数据彼此比较时放置的负载。在A / D转换控制电路中准备对数功能。在从比较器输出脉冲的定时，对数功能在12位数/模转换器中锁存计数器的输出，以确定写入数据寄存器组的数据。在与ADCR中的日志输出相关的设置项目设置为1的情况下，不仅将12位数/模转换器的输出，还将MTU的定时器计数器的输出锁存为日志。

14. 发明授权

US09093320B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US09093320B2
公开(公告)日：2015-07-28
申请号：US14560447
申请日：2014-12-04
申请人： Renesas Electronics Corporation
发明人： Shoji Shukuri
IPC分类号： H01L29/66 , H01L27/115 , H01L23/535
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.
摘要翻译：半导体装置，包括在半导体衬底上具有第一栅极绝缘膜的存储单元，在第一栅极绝缘膜上方的控制栅极电极，在衬底上的第二栅极绝缘膜和控制栅电极的侧壁，存储栅电极在通过第二栅极绝缘膜与控制栅电极相邻布置的第二栅极绝缘膜上，分别位于控制栅电极侧和存储栅极侧的基板中的第一和第二半导体区域，第二栅极绝缘膜具有第一膜，在第一膜上方的电荷存储膜和第二膜上的第三膜，第一膜具有在基板和存储栅电极之间的第一部分，并且厚度大于第二部分之间的厚度栅电极和存储栅电极。

15. 发明授权

US08569136B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US08569136B2
公开(公告)日：2013-10-29
申请号：US13438972
申请日：2012-04-04
申请人： Itaru Kanno
发明人： Itaru Kanno
IPC分类号： H01L21/8234
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823814 , H01L21/823864 , H01L29/6653
摘要： A manufacturing method of a semiconductor device is provided which can improve the performance of the semiconductor device. Ion implantation is applied to nMIS regions 1A and 1B and pMIS regions 1C and 1D of a semiconductor substrate 1 with offset spacers formed over sidewalls of gate electrodes GE1, GE2, GE3, and GE4 to thereby form extension regions for source and drain. In this case, a different photoresist pattern is used for each of the nMIS regions 1A and 1B and the pMIS regions 1C and 1D to individually perform the corresponding ion implantation. Every time the photoresist pattern is re-created, the offset spacer is also re-created.
摘要翻译：提供一种可以提高半导体器件的性能的半导体器件的制造方法。将离子注入施加到半导体衬底1的nMIS区域1A和1B以及pMIS区域1C和1D，其中半导体衬底1具有形成在栅电极GE1，GE2，GE3和GE4的侧壁上的偏移间隔物，从而形成用于源极和漏极的延伸区域。在这种情况下，对于nMIS区域1A和1B以及pMIS区域1C和1D中的每一个使用不同的光致抗蚀剂图案来单独执行相应的离子注入。每次重新制造光致抗蚀剂图案时，也重新创建偏移间隔物。

16. 发明授权

US08564998B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08564998B2
公开(公告)日：2013-10-22
申请号：US13459017
申请日：2012-04-27
申请人： Kazunari Inoue
发明人： Kazunari Inoue
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： Array area and power consumption are reduced in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
摘要翻译：内容可寻址存储器中的阵列区域和功耗降低。通常为多个条目提供用于执行匹配确定和大小确定的比较器，每个条目存储要检索的数据。每个条目包括用于存储数据的数据存储单元和用于存储掩码位的掩码单元。掩模单元的数量小于数据存储单元的数量。搜索数据通过搜索数据总线传送到比较器。根据预定规则选择其中一个条目。比较器对掩码位进行解码，产生掩码指令信号，并且在搜索数据和存储在所选条目中的要检索的数据之间进行匹配比较和大小比较。

17. 发明授权

US08379455B2 Nonvolatile semiconductor storage device including failure detection circuit and method of detecting failure on nonvolatile semiconductor storage device 有权
标题翻译：包括故障检测电路和非易失性半导体存储装置中的故障检测方法的非易失性半导体存储装置
公开(公告)号：US08379455B2
公开(公告)日：2013-02-19
申请号：US13019316
申请日：2011-02-02
申请人： Yoshikazu Kuroda
发明人： Yoshikazu Kuroda
IPC分类号： G11C11/34
CPC分类号： G11C29/12 , G11C16/04 , G11C29/50 , G11C29/50004 , G11C2029/1202
摘要： A nonvolatile semiconductor storage device includes: a word line; a reading circuit; and a failure detection circuit. The word line is connected to gates of a plurality of nonvolatile memory cell transistors. The reading circuit is connected to one end of the word line and supplies one of a reading selection voltage and a reading non-selection voltage to the word line. The failure detection circuit is connected to the other end of the word line and detects a voltage of the word line supplied with the one of the reading selection voltage and the reading non-selection voltage by comparing the voltage with a plurality of reference voltages.
摘要翻译：非易失性半导体存储装置包括：字线; 阅读电路; 和故障检测电路。字线连接到多个非易失性存储单元晶体管的栅极。读取电路连接到字线的一端，并将一个读取选择电压和非读取电压中的一个提供给字线。故障检测电路与字线的另一端连接，通过将电压与多个基准电压进行比较来检测通过读取选择电压和读取非选择电压之一提供的字线的电压。

18. 发明授权

US07920613B2 Optical semiconductor device and method of manufacturing same 有权
标题翻译：光半导体装置及其制造方法
公开(公告)号：US07920613B2
公开(公告)日：2011-04-05
申请号：US12245780
申请日：2008-10-06
申请人： Yasutaka Sakata
发明人： Yasutaka Sakata
IPC分类号： H01S5/00
CPC分类号： H01S5/3434 , B82Y20/00 , H01S5/2226 , H01S5/2275 , H01S5/3054 , H01S2304/00 , H01S2304/04
摘要： The reliability of a buried hetero-structure semiconductor laser is improved by preventing an increase in oscillation threshold current and a decrease in external differential quantum efficiency in cases where the semiconductor laser is energized continuously under conditions of high temperature and high optical output. An optical semiconductor laser has an optical waveguide structure comprising an n-type cladding layer, an active layer and p-type cladding layers, and a current narrowing/blocking structure comprising a p-type blocking layer and an n-type blocking layer, wherein concentration of hydrogen contained in the p-type cladding layers is higher than concentration of hydrogen contained in the p-type blocking layer.
摘要翻译：在半导体激光器在高温和高光输出条件下连续通电的情况下，通过防止振荡阈值电流的增加和外部微分量子效率的降低，可以提高掩埋异质结构半导体激光器的可靠性。光半导体激光器具有包括n型包覆层，有源层和p型覆层的光波导结构以及包括p型阻挡层和n型阻挡层的电流窄化/阻挡结构，其中 p型包覆层中所含的氢的浓度高于p型阻挡层中所含的氢浓度。

19. 发明授权

US11709786B2 Device and method of secure decryption by virtualization and translation of physical encryption keys 有权
公开(公告)号：US11709786B2
公开(公告)日：2023-07-25
申请号：US17404543
申请日：2021-08-17
申请人： Renesas Electronics Corporation
发明人： Ahmad Nasser , Eric Winder
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F12/145 , G06F12/1425 , G06F12/1475
摘要： Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.

20. 发明授权

US09123391B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09123391B2
公开(公告)日：2015-09-01
申请号：US14082320
申请日：2013-11-18
申请人： Renesas Electronics Corporation
发明人： Tetsuo Fukushi , Atsunori Hirobe , Toshikatsu Jinbo , Muneaki Matsushige
IPC分类号： G11C5/02 , G11C11/4097 , G11C7/14
CPC分类号： G11C5/025 , G11C5/02 , G11C5/14 , G11C7/06 , G11C7/14 , G11C11/4091 , G11C11/4097
摘要： A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.
摘要翻译：根据本发明的半导体存储装置1包括第一存储区域11-1和第二存储区域11-2。存储单元MC_m_n和位线BL1，BL2_，。。。。 BLm_被布置在第一和第二存储区域11-1和11-2之间的边界区域18中。设置在边界区域18中的存储单元MC_m_n包括其中没有写入数据的存储单元，并且当从顶部观看边界区域18时，在与边界区域18中重叠的存储单元重叠的位置处形成行56。结果，可以增加存储单元阵列的集成密度并在存储单元阵列中提供一行。

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