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11. 发明授权

US07853738B2 Efficient load/store buffer memory management in a computer communications network data transmission switch 有权
标题翻译：有效的加载/存储缓冲存储器管理在计算机通信网络数据传输交换机中
公开(公告)号：US07853738B2
公开(公告)日：2010-12-14
申请号：US12191364
申请日：2008-08-14
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F13/385
摘要： A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a “load intensive” device or as a “store intensive” device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the “outbound” and “inbound” buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either “load intensive” or “store intensive” mode. The invention is applicable for use with all types of communications network switches (i.e. “Bridges”, “Hubs”, “Routers” etc.).
摘要翻译：公开了一种用于观察连接到计算机通信网络数据传输交换机的外围设备中的数据移动模式的技术，以便（统计）确定外围设备是否被用作“负载密集型”设备或作为“商店密集型”设备（或既不是类型）在规定的时间段内。该设置用于动态调整（并重新分配）分配给连接到外围设备的交换机传输端口的“出站”和“入站”缓冲存储器大小，在该设备以“负载密集型”或 “店铺密集”模式。本发明适用于所有类型的通信网络交换机（即“桥接”，“集线器”，“路由器”等）。

12. 发明申请

US20100011169A1 CACHE MEMORY 失效
标题翻译：高速缓存存储器
公开(公告)号：US20100011169A1
公开(公告)日：2010-01-14
申请号：US12169091
申请日：2008-07-08
申请人： Anil Pothireddy
发明人： Anil Pothireddy
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of the cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous access request.
摘要翻译：公开了一种缓存存储器，设计结构以及用于改进高速缓存性能的相应方法，其包括一个或多个相同大小的高速缓存行，每个高速缓存行适于响应来自处理器的访问请求而存储来自主存储器的数据的高速缓存块 ; 以及大小等于高速缓存线的大小的预测缓冲器，被配置为响应于使用至少一个先前访问请求生成的预测获取信号来存储来自所述主存储器的下一个数据块。

13. 发明申请

US20090158105A1 IN SYSTEM DIAGNOSTICS THROUGH SCAN MATRIX 失效
标题翻译：通过扫描矩阵进行系统诊断
公开(公告)号：US20090158105A1
公开(公告)日：2009-06-18
申请号：US11958468
申请日：2007-12-18
申请人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
发明人： Baalaji Ramamoorthy Konda , Kenneth Pichamuthu , Jayashri Arsikere Basappa , Anil Pothireddy
IPC分类号： G01R31/3185 , G06F11/26
CPC分类号： G06F11/267 , G01R31/318555
摘要： A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.
摘要翻译：公开了一种通过扫描矩阵进行系统诊断的方法，以及执行诊断的集成电路芯片。所述集成电路芯片可操作在多个边界扫描测试模式中，其中所述集成电路芯片中的至少一部分电路被测试，所述集成电路芯片包括扫描矩阵控制器和指令寄存器。提供扫描矩阵控制器用于将所述电路划分成多个矩阵，每个矩阵具有多个扫描元件。提供指令寄存器用于保持扫描矩阵控制器的指令，用于将芯片划分为所述多个矩阵。扫描矩阵控制器还被布置为通过将测试信号施加到电路的测试部分来根据指令寄存器中的指令来测试每个所述矩阵。

14. 发明授权

US08902750B2 Translating between an ethernet protocol and a converged enhanced ethernet protocol 有权
标题翻译：在以太网协议和融合增强型以太网协议之间进行转换
公开(公告)号：US08902750B2
公开(公告)日：2014-12-02
申请号：US13150507
申请日：2011-06-01
申请人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
发明人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
IPC分类号： H04L12/801 , H04L12/26 , H04L29/06 , H04L12/823 , H04L12/835
CPC分类号： H04L47/10 , H04L47/17 , H04L47/30 , H04L47/32 , H04L47/34 , H04L69/08
摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.
摘要翻译：在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

15. 发明授权

US08161366B2 Finite state machine error recovery 失效
标题翻译：有限状态机错误恢复
公开(公告)号：US08161366B2
公开(公告)日：2012-04-17
申请号：US11949305
申请日：2007-12-03
申请人： Anil Pothireddy , Neranjen Ramalingam
发明人： Anil Pothireddy , Neranjen Ramalingam
IPC分类号： G06F11/00
CPC分类号： G06F11/28 , G06F11/0796
摘要： A method and system for using a magnitude comparator circuit and a flag bit, for detecting and preventing errors from occurring in the FSM state bits that could otherwise cause the system to hang. Preferably, the flag bit is set with all the valid state transitions, and a magnitude comparator is used to continuously monitor the value of the current state bits. When a FSM state transition occurs based on the flag bit and the output of the magnitude comparator, a potential error condition can be detected and the FSM transition can be blocked or the FSM can be safely transitioned into a predetermined “reset state”.
摘要翻译：一种使用幅度比较器电路和标志位的方法和系统，用于检测和防止在FSM状态位中发生的错误，否则可能导致系统挂起。优选地，标志位被设置为具有所有有效状态转换，并且使用幅度比较器来连续监视当前状态位的值。当基于标志位和幅度比较器的输出发生FSM状态转换时，可以检测潜在的错误状况，并且可以阻止FSM转换或FSM可以安全地转换到预定的“复位状态”。

16. 发明申请

US20110299394A1 Translating Between An Ethernet Protocol And A Converged Enhanced Ethernet Protocol 有权
标题翻译：在以太网协议和融合增强以太网协议之间进行翻译
公开(公告)号：US20110299394A1
公开(公告)日：2011-12-08
申请号：US13150507
申请日：2011-06-01
申请人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
发明人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/17 , H04L47/30 , H04L47/32 , H04L47/34 , H04L69/08
摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.
摘要翻译：在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

17. 发明申请

US20100134332A1 ENCODING A GRAY CODE SEQUENCE FOR AN ODD LENGTH SEQUENCE 有权
标题翻译：为ODD长度序列编码灰度代码序列
公开(公告)号：US20100134332A1
公开(公告)日：2010-06-03
申请号：US12699153
申请日：2010-02-03
申请人： Jayashri A. Basappa , Anil Pothireddy , David Grant Wheeler
发明人： Jayashri A. Basappa , Anil Pothireddy , David Grant Wheeler
IPC分类号： H03M7/16
CPC分类号： H03M7/16
摘要： A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.
摘要翻译：提供了一种装置，用于从具有长度“L”的二进制值序列生成灰度代码序列。因此，本发明的一个方面提供了一种电路，包括一个循环标志触发电路，其被配置为在第一值和第二值之间切换循环标志;耦合到循环标志触发电路的输出的中间值发生器，二进制值，并且被配置为从循环标志和二进制值生成中间值，以及耦合到中间值生成器的输出的二进制到灰色转换器，被配置为将中间值转换为灰度代码。

18. 发明授权

US07667629B2 Generating a gray code for an odd length sequence using a virtual space 失效
标题翻译：使用虚拟空间生成奇数长度序列的灰色代码
公开(公告)号：US07667629B2
公开(公告)日：2010-02-23
申请号：US12127179
申请日：2008-05-27
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/04
CPC分类号： H03M7/16
摘要： Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.
摘要翻译：使用虚拟空间生成奇数长度序列的灰度计数的方法。可以为给定的奇数多个虚拟域生成多于一组的格雷码，这些域有助于实现容错的更强大的系统。这里广泛考虑的是使用简单而优雅的算法，其较不复杂并且仅使用N位序列。

19. 发明申请

US20100042762A1 Efficient Load/Store Buffer Memory Management in a Computer Communications Network Data Transmission Switch 有权
标题翻译：在计算机通信网络数据传输交换机中高效加载/存储缓冲存储器管理
公开(公告)号：US20100042762A1
公开(公告)日：2010-02-18
申请号：US12191364
申请日：2008-08-14
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , Gopikrishnan Viswanadhan , Neranjen Ramalingam
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a “load intensive” device or as a “store intensive” device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the “outbound” and “inbound” buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either “load intensive” or “store intensive” mode. The invention is applicable for use with all types of communications network switches (i.e. “Bridges”, “Hubs”, “Routers” etc.).
摘要翻译：公开了一种用于观察连接到计算机通信网络数据传输交换机的外围设备中的数据移动模式的技术，以便（统计）确定外围设备是否被用作“负载密集型”设备或作为“商店密集型”设备（或既不是类型）在规定的时间段内。该设置用于动态调整（并重新分配）分配给连接到外围设备的交换机传输端口的“出站”和“入站”缓冲存储器大小，在该设备以“负载密集型”或 “店铺密集”模式。本发明适用于所有类型的通信网络交换机（即“桥接”，“集线器”，“路由器”等）。

20. 发明申请

US20090295608A1 GENERATING A GRAY CODE FOR AN ODD LENGTH SEQUENCE USING A VIRTUAL SPACE 失效
标题翻译：使用虚拟空间生成ODD长度序列的灰度代码
公开(公告)号：US20090295608A1
公开(公告)日：2009-12-03
申请号：US12127179
申请日：2008-05-27
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/16
CPC分类号： H03M7/16
摘要： Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.
摘要翻译：使用虚拟空间生成奇数长度序列的灰度计数的方法。可以为给定的奇数多个虚拟域生成多于一组的格雷码，这些域有助于实现容错的更强大的系统。这里广泛考虑的是使用简单而优雅的算法，其较不复杂并且仅使用N位序列。

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