专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08902750B2 Translating between an ethernet protocol and a converged enhanced ethernet protocol 有权
标题翻译：在以太网协议和融合增强型以太网协议之间进行转换
公开(公告)号：US08902750B2
公开(公告)日：2014-12-02
申请号：US13150507
申请日：2011-06-01
申请人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
发明人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
IPC分类号： H04L12/801 , H04L12/26 , H04L29/06 , H04L12/823 , H04L12/835
CPC分类号： H04L47/10 , H04L47/17 , H04L47/30 , H04L47/32 , H04L47/34 , H04L69/08
摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.
摘要翻译：在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

2. 发明申请

US20110299394A1 Translating Between An Ethernet Protocol And A Converged Enhanced Ethernet Protocol 有权
标题翻译：在以太网协议和融合增强以太网协议之间进行翻译
公开(公告)号：US20110299394A1
公开(公告)日：2011-12-08
申请号：US13150507
申请日：2011-06-01
申请人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
发明人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/17 , H04L47/30 , H04L47/32 , H04L47/34 , H04L69/08
摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.
摘要翻译：在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

3. 发明申请

US20110302481A1 Translation Between A First Communication Protocol And A Second Communication Protocol 失效
标题翻译：第一个通信协议和第二个通信协议之间的翻译
公开(公告)号：US20110302481A1
公开(公告)日：2011-12-08
申请号：US13150486
申请日：2011-06-01
申请人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
发明人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
IPC分类号： H04J3/22 , G06F11/10 , H03M13/09
CPC分类号： H04L69/08 , H03M13/09
摘要： Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.
摘要翻译：在由第一网络组件使用的第一通信协议和由第二网络使用的第二通信协议之间进行翻译，其中转换包括：由独立于第一和第二网络组件的网络引擎适配器接收来自第一和第二网络组件的数据分组第二网络组件; 以及由网络引擎执行基于第一通信协议和第二通信协议的组合通信协议，包括操纵第一通信协议或第二通信协议中的至少一个的数据分组，由此卸载组合的性能要求来自第一和第二网络组件的通信协议。

4. 发明授权

US08589776B2 Translation between a first communication protocol and a second communication protocol 失效
标题翻译：第一通信协议和第二通信协议之间的转换
公开(公告)号：US08589776B2
公开(公告)日：2013-11-19
申请号：US13150486
申请日：2011-06-01
申请人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
发明人： Jean L. Calvignac , Daniel G. Eisenhauer , Ashish A. More , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann
IPC分类号： G06F11/10
CPC分类号： H04L69/08 , H03M13/09
摘要： Translating between a first communication protocol used by a first network component and a second communication protocol used by a second network, where translating includes: receiving, by a network engine adapter operating independently from the first and second network components, data packets from the first and second network components; and performing, by the network engine, a combined communication protocol based on the first communication protocol and the second communication protocol, including manipulating data packets of at least one of the first communication protocol or the second communication protocol, thereby offloading performance requirements for the combined communication protocol from the first and second network components.
摘要翻译：在由第一网络组件使用的第一通信协议和由第二网络使用的第二通信协议之间进行翻译，其中转换包括：由独立于第一和第二网络组件的网络引擎适配器接收来自第一和第二网络组件的数据分组第二网络组件; 以及由网络引擎执行基于第一通信协议和第二通信协议的组合通信协议，包括操纵第一通信协议或第二通信协议中的至少一个的数据分组，由此卸载组合的性能要求来自第一和第二网络组件的通信协议。

5. 发明授权

US08132036B2 Reducing latency in data transfer between asynchronous clock domains 失效
标题翻译：减少异步时钟域之间数据传输的延迟
公开(公告)号：US08132036B2
公开(公告)日：2012-03-06
申请号：US12109483
申请日：2008-04-25
申请人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
IPC分类号： G06F1/12 , H04L7/00 , G06F13/20
CPC分类号： H04L7/0012
摘要： A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.
摘要翻译：公开了用于在以第一时钟频率C1操作的第一时钟域和在第二时钟频率C2操作的第二时钟域之间传送数据的方法和接口电路。根据本发明，数据通过接口电路从第一域发送到第二域。此外，接口电路包括在第三频率C3操作的同步部分，其在一个实施例中大于C2的整数倍。优选地，C3是C2的偶数倍数。在优选实施例中，时钟信号A用于以频率C2操作第二时钟域，并且时钟信号B用于在频率C3处操作接口电路的同步部分，并且时钟信号A和B是源同步的。

6. 发明授权

US07916048B2 Encoding a gray code sequence for an odd length sequence 有权
标题翻译：为奇数长度序列编码灰色码序列
公开(公告)号：US07916048B2
公开(公告)日：2011-03-29
申请号：US12699153
申请日：2010-02-03
申请人： Jayashri A. Basappa , Anil Pothireddy , David G. Wheeler
发明人： Jayashri A. Basappa , Anil Pothireddy , David G. Wheeler
IPC分类号： H03M7/16
CPC分类号： H03M7/16
摘要： A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.
摘要翻译：提供了一种装置，用于从具有长度“L”的二进制值序列生成灰度代码序列。因此，本发明的一个方面提供了一种电路，包括一个循环标志触发电路，其被配置为在第一值和第二值之间切换循环标志;耦合到循环标志触发电路的输出的中间值发生器，二进制值，并且被配置为从循环标志和二进制值生成中间值，以及耦合到中间值生成器的输出的二进制到灰色转换器，被配置为将中间值转换为灰度代码。

7. 发明授权

US08316187B2 Cache memory including a predict buffer 失效
标题翻译：缓存存储器包括预测缓冲区
公开(公告)号：US08316187B2
公开(公告)日：2012-11-20
申请号：US12169091
申请日：2008-07-08
申请人： Anil Pothireddy
发明人： Anil Pothireddy
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of the cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous access request.
摘要翻译：公开了一种缓存存储器，设计结构以及用于改进高速缓存性能的相应方法，其包括一个或多个相同大小的高速缓存行，每个高速缓存行适于响应来自处理器的访问请求而存储来自主存储器的数据的高速缓存块 ; 以及大小等于高速缓存线的大小的预测缓冲器，被配置为响应于使用至少一个先前访问请求生成的预测获取信号来存储来自所述主存储器的下一个数据块。

8. 发明申请

US20090271651A1 Method and System for Reducing Latency in Data Transfer Between Asynchronous Clock Domains 失效
标题翻译：减少异步时钟域之间数据传输延迟的方法和系统
公开(公告)号：US20090271651A1
公开(公告)日：2009-10-29
申请号：US12109483
申请日：2008-04-25
申请人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , David Grant Wheeler
IPC分类号： G06F1/12
CPC分类号： H04L7/0012
摘要： A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock frequency C2. In accordance with this invention, data are transmitted from the first domain, through the interfacing circuitry, and to the second domain. Also, the interfacing circuitry includes a synchronization section that operates at a third frequency C3, which, in one embodiment, is greater than and a whole number multiple of C2. Preferably, C3 is an even whole number multiple of C2. In the preferred embodiment, a clock signal A is used to operate the second clock domain at frequency C2, and a clock signal B is used to operate the synchronization section of the interfacing circuitry at frequency C3, and clock signals A and B are source synchronized.
摘要翻译：公开了用于在以第一时钟频率C1操作的第一时钟域和在第二时钟频率C2操作的第二时钟域之间传送数据的方法和接口电路。根据本发明，数据通过接口电路从第一域发送到第二域。此外，接口电路包括在第三频率C3操作的同步部分，其在一个实施例中大于C2的整数倍。优选地，C3是C2的偶数倍数。在优选实施例中，时钟信号A用于以频率C2操作第二时钟域，并且时钟信号B用于在频率C3处操作接口电路的同步部分，并且时钟信号A和B是源同步的。

9. 发明授权

US07518535B1 Generating a Gray code sequence for any even length using an intermediate binary sequence 失效
标题翻译：使用中间二进制序列生成任何均匀长度的格雷码序列
公开(公告)号：US07518535B1
公开(公告)日：2009-04-14
申请号：US11954451
申请日：2007-12-12
申请人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
发明人： Anil Pothireddy , Jayashri Arsikere Basappa , David Grant Wheeler
IPC分类号： H03M7/04
CPC分类号： H03M7/16
摘要： Generating Gray sequences for non-standard sequence lengths to be used in cyclical sequences having L members. For binary members of the cyclical sequence having values less than L/2 an amount (C/2−L) the most significant bit is forced to a logical “1” to create intermediate binary members. For members greater than or equal to an amount (C/2−L) is added to the binary to create intermediate binaries. The intermediate binaries are then transformed to a Gray code sequence having a non-standard sequence length of L.
摘要翻译：为具有L个成员的循环序列生成用于非标准序列长度的灰色序列。对于具有小于L / 2的数值（C / 2-L）的循环序列的二进制成员，最高有效位被强制为逻辑“1”以创建中间二进制成员。对于大于或等于数量（C / 2-L）的成员添加到二进制文件中以创建中间二进制文件。然后将中间二进制变换为具有非标准序列长度L的格雷码序列。

10. 发明授权

US07500132B1 Method of asynchronously transmitting data between clock domains 失效
标题翻译：在时钟域之间异步传输数据的方法
公开(公告)号：US07500132B1
公开(公告)日：2009-03-03
申请号：US12101939
申请日：2008-04-11
申请人： Anil Pothireddy , Kirtish Karlekar , Grant D. Wheeler
发明人： Anil Pothireddy , Kirtish Karlekar , Grant D. Wheeler
IPC分类号： G06F1/04
CPC分类号： G06F5/06
摘要： A method of asynchronously transmitting data from a first clock domain to a second clock domain by transmitting the data from the first domain to a first register; after a first period of time, transmitting the data from the first register to a second register; after a second period of time, transmitting the data from the second register to a third register; and after a third period of time, transmitting the data from the third register to the second clock domain, where the first clock domain operates at a first frequency C1, and the second clock domain operates at a second frequency C2, C1 being faster than C2; and where: the first period of time is determined by C1; and the second and third periods of time are determined by a third frequency C3 that is greater than and a whole number multiple of C2.
摘要翻译：一种通过将数据从第一域发送到第一寄存器来将数据从第一时钟域异步发送到第二时钟域的方法; 在第一时间段之后，将数据从第一寄存器传送到第二寄存器; 在第二时间段之后，将数据从第二寄存器发送到第三寄存器; 并且在第三时间段之后，将数据从第三寄存器发送到第二时钟域，其中第一时钟域以第一频率C1操作，并且第二时钟域以第二频率C2操作，C1比C2快 ; 其中：第一个时间段由C1决定; 并且第二和第三时间段由大于C2的整数倍的第三频率C3确定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式