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11. 发明申请

US20110145460A1 PROCESSING SYSTEM OPERABLE IN VARIOUS EXECUTION ENVIRONMENTS 有权
标题翻译：处理系统可在各种执行环境中运行
公开(公告)号：US20110145460A1
公开(公告)日：2011-06-16
申请号：US13028416
申请日：2011-02-16
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.
摘要翻译：可在各种执行环境中操作的处理系统。该系统包括具有各自的中断输入的多个处理器核，各自等待中断输出和相应的安全输出。该系统还包括耦合到至少一个处理器核心的寄存器，用于识别主动执行环境。该系统还包括全局中断处理器，其可操作以选择性地将中断路由到所述多个处理器核的一个或多个中断输入。该系统还包括具有多个中断相关输出线的转换电路，并且所述转换电路馈送至少一些所述相应的等待中断输出和相应的安全输出并由所述寄存器馈送。

12. 发明授权

US08117367B2 Processor system with an application and a maintenance function 有权
标题翻译：具有应用和维护功能的处理器系统
公开(公告)号：US08117367B2
公开(公告)日：2012-02-14
申请号：US13028459
申请日：2011-02-16
申请人： Gregory R. Conti , Franck Dahan
发明人： Gregory R. Conti , Franck Dahan
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.
摘要翻译：具有应用程序和维护功能的处理器系统，如果同时执行则会干扰应用程序。处理器系统包括可在不同安全性和上下文相关模式下操作的一组处理器核心，所述处理器具有至少一个中断输入和至少一个等待中断输出。所述处理器系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器核中的至少一个可响应于所述中断信号而可操作以调度在时间上分离的维护功能执行应用程序。

13. 发明授权

US08069290B2 Processing system operable in various execution environments 有权
标题翻译：可在各种执行环境中操作的处理系统
公开(公告)号：US08069290B2
公开(公告)日：2011-11-29
申请号：US13028416
申请日：2011-02-16
申请人： Gregory R. Conti , Franck Dahan
发明人： Gregory R. Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.
摘要翻译：可在各种执行环境中操作的处理系统。该系统包括具有各自的中断输入的多个处理器核，各自等待中断输出和相应的安全输出。该系统还包括耦合到至少一个处理器核心的寄存器，用于识别主动执行环境。该系统还包括全局中断处理器，其可操作以选择性地将中断路由到所述多个处理器核的一个或多个中断输入。该系统还包括具有多个中断相关输出线的转换电路，并且所述转换电路馈送至少一些所述相应的等待中断输出和相应的安全输出并由所述寄存器馈送。

14. 发明申请

US20110145459A1 ELECTRONIC POWER MANAGEMENT SYSTEM 有权
标题翻译：电子电源管理系统
公开(公告)号：US20110145459A1
公开(公告)日：2011-06-16
申请号：US13028440
申请日：2011-02-16
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.
摘要翻译：一种电子电源管理系统，包括可在不同安全性和上下文相关模式下操作的多个处理器，并且具有相应的电源电压输入和时钟输入，所述处理器具有至少一个中断输入和至少一个等待中断输出。该系统还包括功率控制电路，其可操作以可配置地调节所述电源电压输入和时钟输入的电源电压和时钟速率。所述系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器中的至少一个可操作以响应于所述中断信号配置所述功率控制电路。

15. 发明申请

US20090049220A1 INTERRUPT-RELATED CIRCUITS, SYSTEMS, AND PROCESSES 有权
标题翻译：中断相关电路，系统和过程
公开(公告)号：US20090049220A1
公开(公告)日：2009-02-19
申请号：US12100534
申请日：2008-04-10
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic interrupt circuit includes an interrupt-related input line (4235), a security-related status input line (4236), a context-related status input line (4237), and a conversion circuit (4234A) having plural interrupt-related output lines (4245) and selectively operable in response to an interrupt-related signal on said interrupt-related input line (4235) depending on an active or inactive status of each of said security-related status input line (4236) and said context-related status input line (4237).
摘要翻译：电子中断电路包括中断相关输入线（4235），安全相关状态输入线（4236），上下文相关状态输入线（4237）和具有多个中断相关输出的转换电路（4234A）线路（4245），并且根据所述安全相关状态输入线路（4236）和所述上下文相关的每个的活动或不活动状态，响应于所述中断相关输入线路（4235）上的中断相关信号选择性地操作状态输入线（4237）。

16. 发明申请

US20070130482A1 Idle Mode for Power Management 审中-公开
标题翻译：电源管理空闲模式
公开(公告)号：US20070130482A1
公开(公告)日：2007-06-07
申请号：US11559387
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： An apparatus and method for controlling idle mode in an electronic device. In idle mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes a target module coupled to a power and clock control module (PCCM). The PCCM sends an idleack signal to the target module when at least one initiator module within the device is in a power saving mode. When the target module satisfies conditions for idle mode, the target module sends an idleack signal to the PCCM and enters idle mode. In this state, the target module may process information but may not interact with other modules. When the target module detects a wakeup event, a wakeup signal is sent to the PCCM. When the PCCM returns the normal power and clock signal to the target module, the target module may resume normal operation.
摘要翻译：一种用于控制电子设备中的空闲模式的装置和方法。在空闲模式下，电源和时钟信号被减少或停止以节省电力。该装置包括耦合到电源和时钟控制模块（PCCM）的目标模块。当设备中的至少一个启动器模块处于省电模式时，PCCM向目标模块发送空闲信号。当目标模块满足空闲模式的条件时，目标模块向PCCM发送空闲信号并进入空闲模式。在这种状态下，目标模块可以处理信息，但可能不与其他模块交互。当目标模块检测到唤醒事件时，会向PCCM发送唤醒信号。当PCCM向目标模块返回正常的电源和时钟信号时，目标模块可以恢复正常运行。

17. 发明申请

US20070130383A1 Memory Information Transfer Power Management 有权
标题翻译：内存信息传输电源管理
公开(公告)号：US20070130383A1
公开(公告)日：2007-06-07
申请号：US11383416
申请日：2006-05-15
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F13/28
CPC分类号： G06F1/3228 , G06F1/3215 , G06F1/3237 , G06F1/324 , G06F1/325 , G06F1/3275 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.
摘要翻译：一种用于在存储器信息传送系统中节省功率的装置和方法。该系统可以包括耦合到存储器存储设备和外围设备的直接存储器访问（DMA）控制器。 DMA控制器将信息从存储器存储设备传送到外围设备中的缓冲器。 DMA控制器还可以将信息从外围设备中的缓冲器传送到存储器存储设备。当外部设备缓冲区不需要由DMA控制器填充或清空时，DMA控制器进入待机模式。当外围设备缓冲区已满或空时，DMA控制器退出待机模式，清空或填充外围设备缓冲区，并重新进入待机模式。

18. 发明申请

US20070113111A1 Standby Mode for Power Management 有权
标题翻译：电源管理待机模式
公开(公告)号：US20070113111A1
公开(公告)日：2007-05-17
申请号：US11559388
申请日：2006-11-13
申请人： Franck Dahan , Franck Seigneret , Gilles Dubost
发明人： Franck Dahan , Franck Seigneret , Gilles Dubost
IPC分类号： G06F1/00
CPC分类号： G06F1/3237 , G06F1/3228 , Y02D10/128 , Y02D50/20
摘要： An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes an initiator module coupled to a power and clock control module (PCCM). When the initiator module meets conditions for standby mode, the initiator module sends a standby signal to the PCCM and does not interact with other initiator, target, or interconnect modules. When the PCCM communicates a wait signal, the initiator module enters standby mode. When the initiator module detects a wakeup event, the standby signal is deactivated. In this state, the initiator module may process information but may not interact with other modules. When the PCCM deactivates the wait signal and returns power and clock signal to steady state levels, initiator module may resume normal operation.
摘要翻译：一种用于控制电子设备中的待机模式的装置和方法。在待机模式下，电源和时钟信号被减少或停止以节省电力。该装置包括耦合到电源和时钟控制模块（PCCM）的启动器模块。当启动器模块满足待机模式条件时，启动器模块向PCCM发送备用信号，不与其他启动器，目标或互连模块进行交互。当PCCM通信等待信号时，启动器模块进入待机模式。当启动器模块检测到唤醒事件时，待机信号被禁用。在这种状态下，启动器模块可以处理信息，但是可能不与其他模块进行交互。当PCCM关闭等待信号并将电源和时钟信号恢复到稳定状态时，启动器模块可以恢复正常工作。

19. 发明申请

US20120235716A1 ENHANCEMENT OF POWER MANAGEMENT USING DYNAMIC VOLTAGE AND FREQUENCY SCALING AND DIGITAL PHASE LOCK LOOP HIGH SPEED BYPASS MODE 有权
标题翻译：使用动态电压和频率调节和数字相位锁定循环高速旁路模式进行电源管理的增强
公开(公告)号：US20120235716A1
公开(公告)日：2012-09-20
申请号：US13484472
申请日：2012-05-31
申请人： GILLES DUBOST , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： GILLES DUBOST , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/08
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
摘要翻译：一种用于时钟/电压缩放的装置包括：设备功率管理器，被布置为向接口提供可缩放的频率时钟; 由恒定的固定频率时钟和恒定电压提供的延迟锁定环路，被布置成根据过程，电压和/或温度产生唯一的代码; 以及耦合到所述延迟锁定环路的受控延迟线路元件，被布置为基于所述唯一码产生适当的延迟数据选通。一种用于数字锁相环高速旁路模式的方法包括在第一高速时钟域中提供第一数字锁相环; 在第二时钟域中提供第二数字锁相环; 使用本地同步的设备电源管理器根据预选设置来控制第一无毛刺多路复用器的输出; 以及使用所述第二数字锁相环的控制逻辑元件来控制第二无毛刺多路复用器的输出。

20. 发明申请

US20110173363A1 PROCESSOR SYSTEM WITH AN APPLICATION AND A MAINTENANCE FUNCTION 有权
标题翻译：具有应用和维护功能的处理器系统
公开(公告)号：US20110173363A1
公开(公告)日：2011-07-14
申请号：US13028459
申请日：2011-02-16
申请人： Gregory Conti , Franck Dahan
发明人： Gregory Conti , Franck Dahan
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , Y02D10/14
摘要： A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.
摘要翻译：具有应用程序和维护功能的处理器系统，如果同时执行则会干扰应用程序。处理器系统包括可在不同安全性和上下文相关模式下操作的一组处理器核心，所述处理器具有至少一个中断输入和至少一个等待中断输出。所述处理器系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器核中的至少一个可响应于所述中断信号而可操作以调度在时间上分离的维护功能执行应用程序。

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