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11. 发明授权

US06359480B1 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
公开(公告)号：US06359480B1
公开(公告)日：2002-03-19
申请号：US09505204
申请日：2000-02-16
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03L700
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

12. 发明授权

US06326834B1 Pump circuit boosting a supply voltage 失效
标题翻译：泵电路提升电源电压
公开(公告)号：US06326834B1
公开(公告)日：2001-12-04
申请号：US09602896
申请日：2000-06-23
申请人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.
摘要翻译：用于对多个电容器的各个侧面节点进行充电的第一晶体管分别连接到电容器的这些节点。用于输出每个电容器的电荷的第二晶体管分别连接在电容器的相应的一个侧面节点和输出端子之间。用于将电容器的另一侧节点的电荷转移到其他节点的多个第三晶体管连接到相应的其他节点。每个电容器的电荷通过顺序地控制第三晶体管，通过一个路径从高电位的节点被串行地传递到较低电位的节点，或者每个电容器的电荷在高电位的任意节点之间并行传送潜在和低节点通过多个路径。通过这些操作，每个电容器的电荷被再循环。

13. 发明授权

US6154402A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6154402A
公开(公告)日：2000-11-28
申请号：US398201
申请日：1999-09-17
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , G11C7/00
CPC分类号： G11C7/06 , G11C7/12
摘要： In a semiconductor memory device, charge transfer gates and a bit line precharging/equalizing circuit are inserted in the order mentioned in a bit line pair between memory cells and a sense amplifier. When the transfer gates are off, data of the memory cells are read out to the bit line pair located on the memory cell side. Subsequently, when the transfer gates are turned on, the data are transferred to the bit line pair located on the sense amplifier side. Thereafter, the transfer gates are turned off on the basis of a threshold value of the transfer gates. Then, the memory cell data transferred to the sense amplifier side are amplified by a conventional DRAM method. The bit line precharging/equalizing circuit does not require a large area. It is therefore possible to miniaturize the semiconductor memory device.
摘要翻译：在半导体存储器件中，按照存储器单元和读出放大器之间的位线对中所述的顺序插入电荷传输门和位线预充电/均衡电路。当传输门关闭时，存储器单元的数据被读出到位于存储单元侧的位线对。随后，当传输门被接通时，数据被传送到位于读出放大器侧的位线对。此后，基于传送门的阈值关闭传送门。然后，通过传统的DRAM方法放大传送到读出放大器侧的存储单元数据。位线预充电/均衡电路不需要大面积。因此，可以使半导体存储器件小型化。

14. 发明授权

US08582628B2 Transmitting apparatus, receiving apparatus, transmitting/receiving system, and image display system 有权
标题翻译：发送装置，接收装置，发送/接收系统和图像显示系统
公开(公告)号：US08582628B2
公开(公告)日：2013-11-12
申请号：US13148856
申请日：2010-10-20
申请人： Seiichi Ozawa , Hironobu Akita
发明人： Seiichi Ozawa , Hironobu Akita
IPC分类号： H04B1/38
CPC分类号： H04L7/10 , G09G3/2096 , G09G3/3611 , G09G2370/08 , G09G2370/14 , H04L7/0008 , H04L7/0091 , H04L7/0337
摘要： A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.
摘要翻译：接收装置20n的数据接收单元21从发送装置10的数据发送单元11接收校准数据以检测接收装置20n中的数据接收状态或时钟接收状态。解码器单元24使发送单元26 发送通过将校准数据采样获得的采样器单元23的校准样本数据发送到发送设备10.发送设备10的控制单元15基于校准样本来检测接收设备20n中的数据接收状态或时钟接收状态从接收装置20n接收到的数据，并根据检测结果控制数据发送部11和时钟发送部12。

15. 发明申请

US20120306845A1 TRANSMISSION DEVICE, RECEPTION DEVICE, TRANSMISSION-RECEPTION SYSTEM, AND IMAGE DISPLAY SYSTEM 有权
标题翻译：传输设备，接收设备，传输接收系统和图像显示系统
公开(公告)号：US20120306845A1
公开(公告)日：2012-12-06
申请号：US13517462
申请日：2010-12-13
申请人： Seiichi Ozawa , Hironobu Akita
发明人： Seiichi Ozawa , Hironobu Akita
IPC分类号： G09G5/00 , H04L25/02
CPC分类号： G09G3/20 , G09G3/3611 , G09G2300/0426 , G09G2310/08 , G09G2370/08 , H04L25/0264
摘要： Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.
摘要翻译：接收装置201〜20N依次排列成一维。接收装置20n具有数据输入缓冲器21，第一时钟输入缓冲器221和第一时钟输出缓冲器231.第一时钟输入缓冲器221缓冲输入到第一时钟端子P21和P22的时钟，并将其输出到第一时钟输出缓冲器231缓冲从第一时钟输入缓冲器221输入的时钟并将其从第二时钟端子P31和P32输出。数据输入端子P11和P12位于第一时钟端子和第二时钟端子之间。

16. 发明申请

US20120068995A1 TRANSMISSION APPARATUS, RECEPTION APPARATUS, TRANSMISSION-RECEPTION SYSTEM, AND IMAGE DISPLAY SYSTEM 有权
标题翻译：传输装置，接收装置，传输接收系统和图像显示系统
公开(公告)号：US20120068995A1
公开(公告)日：2012-03-22
申请号：US13265083
申请日：2010-04-22
申请人： Seiichi Ozawa , Hironobu Akita
发明人： Seiichi Ozawa , Hironobu Akita
IPC分类号： G06F3/038 , H04L7/00 , H04B15/00 , H04L25/03 , H04L27/06
CPC分类号： H04L7/0008 , G09G3/3611 , G09G2310/08 , G09G2370/08 , H04L7/0091 , H04N5/12 , H04N5/66
摘要： The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection section 25 of a reception apparatus 20n, based on data output from a sampler section 23, both or either of detection of a phase difference between data received by a data reception section 21 and a clock received by a clock reception section 22, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection section 25 is transmitted to a transmission apparatus 10 by a detection signal transmission section 26. In the transmission apparatus 10, by a control section 15, based on the detection signal received by a detection signal reception section 14, both or either of control of adjustment of a phase between data transmitted by a data transmission section 11 and a clock transmitted by a clock transmission section 12, and/or adjustment of an amplitude of the data is performed.
摘要翻译：本发明提供一种易于通过接收装置中的时钟对数据进行正确采样的发送装置和接收装置。在接收装置20n的检测部25中，根据从取样部23输出的数据，检测由数据接收部21接收到的数据与时钟接收部22接收的时钟之间的相位差，和/或该数据的波形失真。表示检测部25的检测结果的检测信号由检测信号发送部26发送到发送装置10.在发送装置10中，通过控制部15，基于由检测信号接收部14，执行由数据发送部11发送的数据与时钟发送部12发送的时钟之间的相位的调整的控制和/或数据的振幅的调整。

17. 发明申请

US20110317747A1 TRANSMITTING APPARATUS, RECEIVING APPARATUS, TRANSMITTING/RECEIVING SYSTEM, AND IMAGE DISPLAY SYSTEM 有权
标题翻译：发送装置，接收装置，发送/接收系统和图像显示系统
公开(公告)号：US20110317747A1
公开(公告)日：2011-12-29
申请号：US13148856
申请日：2010-10-20
申请人： Seiichi Ozawa , Hironobu Akita
发明人： Seiichi Ozawa , Hironobu Akita
IPC分类号： H04B1/38
CPC分类号： H04L7/10 , G09G3/2096 , G09G3/3611 , G09G2370/08 , G09G2370/14 , H04L7/0008 , H04L7/0091 , H04L7/0337
摘要： A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.
摘要翻译：接收装置20n的数据接收单元21从发送装置10的数据发送单元11接收校准数据以检测接收装置20n中的数据接收状态或时钟接收状态。解码器单元24使发送单元26 发送通过将校准数据采样获得的采样器单元23的校准样本数据发送到发送设备10.发送设备10的控制单元15基于校准样本来检测接收设备20n中的数据接收状态或时钟接收状态从接收装置20n接收到的数据，并根据检测结果控制数据发送部11和时钟发送部12。

18. 发明授权

US06731149B2 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
标题翻译：用于产生与时钟信号同步的信号的同步电路
公开(公告)号：US06731149B2
公开(公告)日：2004-05-04
申请号：US10003312
申请日：2001-12-06
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03K501
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.
摘要翻译：用于正向脉冲的第一延迟线和用于反向脉冲的第二延迟线由单位延迟元件组成。状态保持部根据沿着第一延迟线传送的正向脉冲的传送位置来确定第二延迟线上的反向脉冲的输入位置。在构成第一和第二延迟线的单位延迟元件中，可以通过增加与脉冲信号的上升相关的晶体管的电流驱动能力来提高同步精度。

19. 发明授权

US06337834B1 Synchronous signal generation circuit 有权
标题翻译：同步信号发生电路
公开(公告)号：US06337834B1
公开(公告)日：2002-01-08
申请号：US09706842
申请日：2000-11-07
申请人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
发明人： Katsuaki Isobe , Hironobu Akita , Satoshi Eto , Haruki Toda
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/22 , G11C7/222
摘要： The present invention provides a synchronous signal generation circuit that can be operated with a high accuracy, at a high speed and with a low power consumption without being affected by the process dispersion. The synchronous signal generation circuit of the present invention comprises a real circuit including an input receiver, an off-chip driver, and a mirror-type synchronous circuit, and a dummy circuit for determining the delay time in the mirror-type synchronous circuit, the dummy circuit including an input receiver and an off-chip driver. In the dummy circuit, the input signal is supplied first to the off-chip driver and, then, to the input receiver so as to permit the signal between the off-chip driver and the input receiver to be a small amplitude signal. It follows that the real circuit and the dummy circuit are equal to each other in the signal levels in the input and output portions of each of the input receiver and the off-chip driver. The particular construction makes it possible to minimize the error in the delay time between the real circuit and the dummy circuit relative to the process dispersion so as to improve the synchronizing accuracy and, thus, to achieve a high speed I/O.
摘要翻译：本发明提供一种同步信号发生电路，其能够以高精度，高速度且低功耗地操作，而不受处理分散的影响。本发明的同步信号发生电路包括实际电路，其包括输入接收器，片外驱动器和反射镜型同步电路，以及用于确定镜式同步电路中的延迟时间的虚拟电路，虚拟电路包括输入接收器和片外驱动器。在虚拟电路中，首先将输入信号提供给片外驱动器，然后提供给输入接收器，以允许片外驱动器和输入接收器之间的信号为小振幅信号。因此，实际电路和虚拟电路在每个输入接收器和片外驱动器的输入和输出部分的信号电平中彼此相等。该特定结构使得可以将实际电路和虚拟电路之间相对于处理色散的延迟时间的误差最小化，从而提高同步精度，从而实现高速I / O。

20. 发明授权

US06292411B1 Delay control circuit synchronous with clock signal 失效
标题翻译：延时控制电路与时钟信号同步
公开(公告)号：US06292411B1
公开(公告)日：2001-09-18
申请号：US09537424
申请日：2000-03-27
申请人： Masahiro Kamoshida , Hironobu Akita
发明人： Masahiro Kamoshida , Hironobu Akita
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , H03K5/135 , H04L7/0008 , H04L7/0037
摘要： A delay line for forward pulse has a plurality of delay units for forward pulse. A delay line for backward pulse has a plurality of delay units for backward pulse. In the delay line for backward pulse, a pulse signal is propagated in an opposite direction to a direction of the propagation in the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for forward pulse is set to be parallel to a direction of the delay line for forward pulse. A direction from an input terminal to an output terminal in the delay units for backward pulse is set to be parallel to a direction of the delay line for backward pulse. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for forward pulse are set to be opposite to one another. The directions from the input terminal to the output terminal in two adjacent ones of the delay units for backward pulse are set to be opposite to one another.
摘要翻译：用于正向脉冲的延迟线具有用于正向脉冲的多个延迟单元。用于反向脉冲的延迟线具有用于反向脉冲的多个延迟单元。在用于反向脉冲的延迟线中，脉冲信号在与正向脉冲的延迟线中的传播方向相反的方向上传播。用于正向脉冲的延迟单元中的从输入端子到输出端子的方向设置为与正向脉冲的延迟线的方向平行。用于反向脉冲的延迟单元中的从输入端子到输出端子的方向设置为与用于反向脉冲的延迟线的方向平行。从正向脉冲的两个相邻延迟单元中的输入端子到输出端子的方向被设定为彼此相反。在后向脉冲的两个相邻的延迟单元中从输入端子到输出端子的方向被设定为彼此相反。

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