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1. 发明授权

US06731149B2 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
标题翻译：用于产生与时钟信号同步的信号的同步电路
公开(公告)号：US06731149B2
公开(公告)日：2004-05-04
申请号：US10003312
申请日：2001-12-06
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03K501
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.
摘要翻译：用于正向脉冲的第一延迟线和用于反向脉冲的第二延迟线由单位延迟元件组成。状态保持部根据沿着第一延迟线传送的正向脉冲的传送位置来确定第二延迟线上的反向脉冲的输入位置。在构成第一和第二延迟线的单位延迟元件中，可以通过增加与脉冲信号的上升相关的晶体管的电流驱动能力来提高同步精度。

2. 发明授权

US06359480B1 Synchronizing circuit for generating a signal synchronizing with a clock signal 失效
公开(公告)号：US06359480B1
公开(公告)日：2002-03-19
申请号：US09505204
申请日：2000-02-16
申请人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
发明人： Katsuaki Isobe , Tsuneo Inaba , Hironobu Akita
IPC分类号： H03L700
CPC分类号： H03K5/135 , H03K5/133 , H03L7/00
摘要： A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

3. 发明授权

US07800935B2 Resistance change memory device 有权
标题翻译：电阻变化记忆装置
公开(公告)号：US07800935B2
公开(公告)日：2010-09-21
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi Maejima , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 ＆Dgr; R2的关系。

4. 发明申请

US20090109728A1 RESISTANCE CHANGE MEMORY DEVICE 有权
标题翻译：电阻变化存储器件
公开(公告)号：US20090109728A1
公开(公告)日：2009-04-30
申请号：US12252675
申请日：2008-10-16
申请人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
发明人： Hiroshi MAEJIMA , Katsuaki Isobe , Naoya Tokiwa , Satoru Takase , Yasuyuki Fukuda , Hideo Mukai , Tsuneo Inaba
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2211/5642 , G11C2213/11 , G11C2213/34 , G11C2213/56 , G11C2213/72
摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.
摘要翻译：一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 DeltaR2的关系。

5. 发明授权

US6046924A Semiconductor memory device having a sense amplifier region formed in a triple-well structure 有权
标题翻译：具有以三阱结构形成的读出放大器区域的半导体存储器件
公开(公告)号：US6046924A
公开(公告)日：2000-04-04
申请号：US335751
申请日：1999-06-18
申请人： Katsuaki Isobe , Tsuneo Inaba
发明人： Katsuaki Isobe , Tsuneo Inaba
IPC分类号： G11C11/401 , G11C7/06 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C5/02
CPC分类号： G11C11/4091 , G11C7/06 , H01L27/10897
摘要： Sub-cell arrays are formed in p-type cell-forming wells, respectively, with a region between two adjacent sub-cell arrays being formed a sense amplifier circuit region which includes three wells, a first p-type well isolated from the p-type cell-forming wells, and first and second n-type wells for isolating the p-type cell-forming wells, wherein an NMOS sense amplifier is arranged in the first p-type well, a PMOS sense amplifier and a first switch circuit are arrange in one of the first and second n-type wells and a bit line equalizer circuit and a second switch circuit are arranged in the other of the first and second n-type well.
摘要翻译：子电池阵列分别形成在p型电池形成阱中，其中两个相邻子电池阵列之间的区域形成读出放大器电路区域，该区域包括三个阱，第一p型阱，用于隔离p型电池形成阱的第一和第二n型阱，其中NMOS读出放大器布置在第一p型阱中，PMOS读出放大器和第一开关电路是排列在第一和第二n型阱中的一个中，位线均衡器电路和第二开关电路布置在第一和第二n型阱中的另一个中。

6. 发明授权

US09741434B2 Resistance change memory 有权
公开(公告)号：US09741434B2
公开(公告)日：2017-08-22
申请号：US14018287
申请日：2013-09-04
申请人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
发明人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
IPC分类号： G11C5/06 , G11C13/00 , G11C11/16
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

7. 发明授权

US09183951B2 Resistance change memory and test method of the same 有权
标题翻译：电阻变化记忆和测试方法相同
公开(公告)号：US09183951B2
公开(公告)日：2015-11-10
申请号：US14201534
申请日：2014-03-07
申请人： Tsuneo Inaba , Dong Keun Kim
发明人： Tsuneo Inaba , Dong Keun Kim
IPC分类号： G11C13/00 , G11C29/12 , G11C8/08 , G11C29/06 , G11C29/50 , G11C11/16
CPC分类号： G11C29/12005 , G11C8/08 , G11C11/16 , G11C11/1675 , G11C13/0004 , G11C13/0069 , G11C29/06 , G11C29/50008 , G11C2013/009 , G11C2029/1202
摘要： According to one embodiment, a resistance change memory includes a memory cell array, an address counter, a word line driver, a power supply circuit, and a write driver. Memory cells include resistive storage elements and cell transistors. The power supply circuit generates a stress voltage different from a power supply voltage used to write data into the memory cells in a normal operation. The write driver applies the stress voltage across first bit and source lines to pass a stress current through the memory cell selected by a first word line. The write driver applies the stress voltage across second bit and source lines to pass the stress current through the memory cell selected by a second word line.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元阵列，地址计数器，字线驱动器，电源电路和写入驱动器。存储单元包括电阻存储元件和单元晶体管。电源电路产生与用于在正常操作中将数据写入存储单元的电源电压不同的应力电压。写驱动器将应力电压施加在第一位和源极线之间以将应力电流传递通过由第一字线选择的存储单元。写驱动器将应力电压施加在第二位和源极线之间，以使应力电流通过由第二字线选择的存储单元。

8. 发明授权

US08947920B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08947920B2
公开(公告)日：2015-02-03
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
发明人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译：根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。

9. 发明授权

US08274826B2 NAND type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：US08274826B2
公开(公告)日：2012-09-25
申请号：US12838867
申请日：2010-07-19
申请人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
发明人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
IPC分类号： G11C16/04
CPC分类号： G11C16/06
摘要： According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.
摘要翻译：根据一个实施例，NAND型闪速存储器包括设置在第一和第二存储器平面之间的第一传输晶体管，第一传输晶体管的第一电位传输端共同连接到第一NAND块中的第一字线，第二字配置在第三NAND块中的第二转移晶体管，设置在第一存储器平面的第一端的第二转移晶体管，第二转移晶体管的第一电位转移端连接到第二NAND块中的第三字线，以及第三转移晶体管设置在第二存储器平面的第二端，第三传输晶体管的第一电位传输端连接到第四NAND块中的第四字线。

10. 发明授权

US08120948B2 Data writing method for magnetoresistive effect element and magnetic memory 有权
标题翻译：磁阻效应元件和磁存储器的数据写入方法
公开(公告)号：US08120948B2
公开(公告)日：2012-02-21
申请号：US12561495
申请日：2009-09-17
申请人： Masahiko Nakayama , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
发明人： Masahiko Nakayama , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1675
摘要： A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer.
摘要翻译：一种用于本发明一个方面的磁阻效应元件的数据写入方法，包括产生写入电流，其中从下降沿开始到下降沿结束的下降周期长于从开始上升沿到上升沿结束，并且使写入电流流过磁阻效应元件，该磁阻效应元件包括具有不变磁化方向的第一磁性层，具有可变磁化方向的第二磁性层和设置在可变磁化方向之间的隧道势垒层，第一磁性层和第二磁性层，以改变第二磁性层的磁化方向。

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