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11. 发明申请

US20120075363A1 PIXEL AND ORGANIC LIGHT EMITTING DISPLAY USING THE SAME 有权
标题翻译：使用相同的像素和有机发光显示
公开(公告)号：US20120075363A1
公开(公告)日：2012-03-29
申请号：US13118149
申请日：2011-05-27
申请人： Hyung-Soo Kim
发明人： Hyung-Soo Kim
IPC分类号： G09G3/32 , G09G5/10 , H01L51/52
CPC分类号： G09G3/2022 , G09G3/3225 , G09G2300/0814 , G09G2310/061 , H01L27/3244
摘要： A pixel of an organic light emitting display in which the pixel includes: a first transistor including a first electrode coupled to a first power source, a second electrode, and a gate electrode coupled to a first node; a second transistor including a first electrode coupled to a third power source, a second electrode coupled to the first node, and a gate electrode coupled to a reset control line; a third transistor including a first electrode coupled to the first node, a second electrode coupled to a fourth power source, and a gate electrode; a fourth transistor including a first electrode coupled to the gate electrode of the third transistor, a second electrode coupled to a scan line, and a gate electrode coupled to a data line; and an organic light emitting diode (OLED) including an anode electrode coupled to the second electrode of the first transistor, and a cathode electrode coupled to a second power source.
摘要翻译：有机发光显示器的像素包括：第一晶体管，包括耦合到第一电源的第一电极，第二电极和耦合到第一节点的栅电极; 第二晶体管，包括耦合到第三电源的第一电极，耦合到第一节点的第二电极和耦合到复位控制线的栅电极; 第三晶体管，包括耦合到第一节点的第一电极，耦合到第四电源的第二电极和栅电极; 第四晶体管，包括耦合到第三晶体管的栅电极的第一电极，耦合到扫描线的第二电极和耦合到数据线的栅电极; 以及包括耦合到第一晶体管的第二电极的阳极电极和耦合到第二电源的阴极电极的有机发光二极管（OLED）。

12. 发明授权

US08099620B2 Domain crossing circuit of a semiconductor memory apparatus 失效
标题翻译：半导体存储装置的域交叉电路
公开(公告)号：US08099620B2
公开(公告)日：2012-01-17
申请号：US12346675
申请日：2008-12-30
申请人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hae Rang Choi , Yong Ju Kim , Sung Woo Han , Hee Woong Song , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： G06F1/00 , G06F1/04 , G06F12/00 , H03K19/00 , H03L7/00 , G11C8/00
CPC分类号： G11C7/1051 , G06F1/12 , G11C7/1072 , G11C7/222
摘要： A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.
摘要翻译：半导体存储器装置的域交叉电路，域交叉电路包括在基本上相同的时钟周期产生的第一和第二计数信号，并且相对于相同位组合数据参考内部时钟信号表示预定的时钟差，以及数据处理单元，被配置为响应于与外部时钟信号同步的输入数据，基于第二计数信号提供对应于输入数据的输出数据。

13. 发明授权

US08035431B2 Delay locked loop and delay locking method having burst tracking scheme 有权
标题翻译：具有脉冲串跟踪方案的延迟锁定环路和延迟锁定方法
公开(公告)号：US08035431B2
公开(公告)日：2011-10-11
申请号：US12494509
申请日：2009-06-30
申请人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/093
摘要： A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.
摘要翻译：延迟锁定环（DLL）包括复制延迟单元，其被配置为延迟输出时钟以产生反馈时钟; 相位检测器，被配置为测量反馈时钟和输入时钟之间的相位差; 量化单元，被配置为量化由相位检测器测量的相位差; 以及延迟单元，被配置为基于来自量化单元的量化结果来延迟输入时钟，以产生输出时钟。

14. 发明授权

US08035418B2 Output driver 有权
标题翻译：输出驱动
公开(公告)号：US08035418B2
公开(公告)日：2011-10-11
申请号：US12832167
申请日：2010-07-08
申请人： Ic-Su Oh , Hyung-Soo Kim , Chang-Kun Park
发明人： Ic-Su Oh , Hyung-Soo Kim , Chang-Kun Park
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output driver of a semiconductor device includes driving transistors and a body bias providing unit. The driving transistors are coupled in parallel and configured to drive an output terminal. The body bias providing unit is configured to supply the driving transistors with respective body biases of at least two levels.
摘要翻译：半导体器件的输出驱动器包括驱动晶体管和体偏置提供单元。驱动晶体管并联耦合，并配置成驱动输出端。身体偏置提供单元被配置为向驱动晶体管提供至少两个级别的相应身体偏置。

15. 发明申请

US20110241726A1 ON-DIE TERMINATION CIRCUIT 有权
标题翻译：端子终止电路
公开(公告)号：US20110241726A1
公开(公告)日：2011-10-06
申请号：US13012972
申请日：2011-01-25
申请人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Hyung Soo KIM , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
摘要翻译：片上终端电路包括：参考周期信号生成电路，其根据参考电压的电平生成基准周期信号;第一周期信号生成电路，其根据电压的电平生成第一周期信号; 周期比较电路，其将第一周期信号的周期与基准周期信号的周期进行比较，并计数多个驱动信号;以及驱动器电路，其响应于多个驱动信号而驱动该焊盘。

16. 发明授权

US08023356B2 Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same 失效
标题翻译：半导体存储装置的电压电平比较电路，使用电压电平比较电路的电压调整电路和使用其的半导体存储装置
公开(公告)号：US08023356B2
公开(公告)日：2011-09-20
申请号：US12336423
申请日：2008-12-16
申请人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
发明人： Ic-Su Oh , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee , Jae-Min Jang , Chang-Kun Park
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.
摘要翻译：半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及电压产生单元，被配置为根据检测信号的电位来驱动外部电压并输出外部电压作为输出电压。

17. 发明授权

US08013593B2 Voltage measuring apparatus for semiconductor integrated circuit and voltage measuring system having the same 有权
标题翻译：具有该半导体集成电路和电压测量系统的电压测量装置
公开(公告)号：US08013593B2
公开(公告)日：2011-09-06
申请号：US11961988
申请日：2007-12-20
申请人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
发明人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
IPC分类号： G01R25/00
CPC分类号： G01R31/3004 , G01R29/26
摘要： A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
摘要翻译：一种用于半导体集成电路的电压测量装置包括：第一延迟单元，被配置为延迟第一区域中的参考时钟;第二延迟单元，被配置为在第二区域中延迟参考时钟;以及分析单元，被配置为分析电压差基于与由第一延迟单元和第二延迟单元生成的延迟时钟信号相关联的相位，区域之间的电平。

18. 发明授权

US07990785B2 Delay locked loop circuit of semiconductor device 有权
标题翻译：半导体器件的延迟锁定环路
公开(公告)号：US07990785B2
公开(公告)日：2011-08-02
申请号：US12262517
申请日：2008-10-31
申请人： Hee-Woong Song , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
发明人： Hee-Woong Song , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Ji-Wang Lee
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C7/22 , G11C7/222 , G11C29/023 , G11C29/028 , H03L7/0812 , H03L7/089 , H03L7/095
摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.
摘要翻译：半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。

19. 发明申请

US20110128268A1 ORGANIC LIGHT EMITTING DISPLAY 有权
标题翻译：有机发光显示
公开(公告)号：US20110128268A1
公开(公告)日：2011-06-02
申请号：US12836528
申请日：2010-07-14
申请人： Hyung-Soo KIM , Soon-Sung AHN
发明人： Hyung-Soo KIM , Soon-Sung AHN
IPC分类号： G09G5/00
CPC分类号： G09G3/3225 , G09G2300/0426 , G09G2320/0223 , G09G2320/0233 , G09G2320/0242 , G09G2330/02 , G09G2330/06 , H01L27/3211 , H01L27/3279
摘要： An organic light emitting display includes an image display unit having a plurality of pixels, and first and second pixel power lines that receive pixel-driving voltages from first and second power supplies, respectively. The second pixel power lines are interleaved with the first pixel power lines. Adjacent pixels of the same color from among the plurality of pixels provided in the image display unit are coupled to pixel power lines corresponding to different power supplies. This is to solve or mitigate the problem of non-uniform brightness of the entire image display unit due to voltage drops in the pixel power lines.
摘要翻译：有机发光显示器包括具有多个像素的图像显示单元和分别从第一和第二电源接收像素驱动电压的第一和第二像素电力线。第二像素电力线与第一像素电力线交错。来自图像显示单元中提供的多个像素中的相同颜色的相邻像素耦合到对应于不同电源的像素电力线。这是为了解决或减轻由于像素电力线中的电压降而引起的整个图像显示单元的不均匀亮度的问题。

20. 发明授权

US07949081B2 Phase detecting circuit and clock generating apparatus including the same 有权
标题翻译：相位检测电路和包括该相位检测电路的时钟发生装置
公开(公告)号：US07949081B2
公开(公告)日：2011-05-24
申请号：US12026384
申请日：2008-02-05
申请人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
发明人： Hee Woong Song , Kun Woo Park , Yong Ju Kim , Jong Woon Kim , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang
IPC分类号： H04L7/04 , H03L7/00
CPC分类号： H03L7/0814 , H03L7/089
摘要： A phase detecting circuit includes a first node that outputs a pull-up control signal, a second node that outputs a pull-down control signal, an initializing unit that initializes voltage levels of the first and second nodes in response to a pre-charge signal, a data input unit to which receives a receiver data, a phase comparison unit that compares a phase of a receiver clock and a phase of the receiver data input to the data input unit to control the voltage levels of the first and second nodes, and a charging/discharging unit that charges or discharges electric charges that are applied to the first and second nodes.
摘要翻译：相位检测电路包括：输出上拉控制信号的第一节点，输出下拉控制信号的第二节点;响应于预充电信号初始化第一和第二节点的电压电平的初始化单元; 接收接收机数据的数据输入单元，比较接收机时钟的相位和输入到数据输入单元的接收机数据的相位以控制第一和第二节点的电压电平的相位比较单元，以及充电/放电单元，其对施加到第一和第二节点的电荷进行充电或放电。

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